Charge trapping characterization of MOCVD HfO2/p-Si interfaces at cryogenic temperatures

The paper focuses on the study of charge trapping processes in high-k MOS structures at cryogenic temperatures. It was shown, that there is extremely strong trapping in shallow electron and hole traps, localized in the high-k dielectrics. Concentration of shallow electron traps is as much as 10¹³ cm⁻², while abnormal small capture cross-sections (4.5–8 × 10⁻²⁴ cm² for different samples, accordingly) suggests localization of shallow emitting electron traps in transition layer “high-k dielectric/Si”, more, than at the interface. Shallow hole traps with concentration near 10¹² cm⁻² are separated from silicon valence band with energy barrier in the range 10–39 meV for different samples.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Breakdown fields and conduction mechanisms in thin Ta2O5 layers on Si for high density DRAMs

The conduction mechanisms and the microstructure of rf sputtered Ta₂O₅ on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated. The as-deposited and annealed at 873 K layers are amorphous whereas crystalline Ta₂O₅ (orthorhombic β-Ta₂O₅ phase) was obtained after O₂ treatment at 1123 K. The results (electrical, X-ray diffraction, transmission electron microscopy) reveal the formation of an interfacial ultrathin SiO₂ layer under all technological regimes used. The higher (493 K) substrate temperature during deposition stimulates the formation of amorphous rather than crystalline SiO₂. It is found that the oxygen heating significantly reduces the oxide charge (Q_f<10¹⁰ cm⁻²) and improves the breakdown characteristics (the effect is more pronounced for the higher annealing temperature). It is accompanied by an increase of the effective dielectric constant (up to 37 after 1123 K treatment). It is established that the influence of the oxygen treatment on the leakage current is different depending on the film thickness, namely: a beneficial effect for the thinner and a deterioration of leakage characteristics for thicker (80 nm) films. A leakage current density as low as 10⁻⁷ A/cm² at 1 MV/cm applied field for 26 nm annealed layers has been obtained. The current reduction is considered to be due to a removal by annealing of certain structural nonperfections present in the initial layers. Generally, the results are discussed in terms of simultaneous action of two opposite and competing processes taking place at high temperatures––a real annealing of defects and an appearance of a crystal phase and/or a neutral traps generation. The contribution of the neutral traps also is involved to explain the observed weaker charge trapping in the as-fabricated films compared to the annealed ones.The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

Bulk oxide charge and slow states in Si–SiO2 structures generated by RIE-mode plasma

The damage induced in the thin SiO₂–Si system after an exposure to O₂ and N₂ plasma working in reactive ion etching (RIE) mode has been studied. A generation of high density (up to 5×10¹² cm⁻² in the first 15 s plasma exposure) of positive oxide charge in bulk traps as well as in slow states has been established. The RIE damage effects become highly process dependent as the plasma time increases, the fixed oxide charge first increases and then slows down or even turns around depending on discharge conditions. It is suggested that the relative contribution of the two main plasma components (ion bombardment and vacuum UV photons) at different discharge regimes is the reason for the appearance or the absence of the “turn-around” effect. It is established that the combination O₂ plasma and low pressure is critical for the degradation of the plasma treated samples. The results reveal a strong linear correlation between the leakage current detected and plasma created positive charge.     

Electrical stress and plasma-induced traps in SiO2

High field stress and N₂ reactive ion etching (RIE)-mode plasma-generated positive oxide charge in thin (13 nm) SiO₂–Si structures have been studied. A threshold field of about 8.5–9 MV/cm for positive charge formation is found. It is established that both high field stress and RIE-like plasma treatment create nonuniformly distributed positive charge in the depth of the oxide, in the form of bulk traps and slow states. It is found that the generation of neutral bulk traps is an attribute, only of the high field stressing. The structural nature of the process-induced traps is discussed. It is suggested that the impact ionization of oxygen vacancies accounts for the positive charge and neutral trap creation.     

Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.     

Constant current stress-induced leakage current in mixed HfO2-Ta2O5 stacks

The electrical characteristics of HfO₂-Ta₂O₅ mixed stacks under constant current stress (CCS) at gate injection with 20 mA/cm² and stressing times of 50 and 200 s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes - positive charge build-up and new bulk traps generation - are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO₂ layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta₂O₅-HfO₂-based capacitors.     

Optical and electrical characterization of the electron beam gun evaporated TiO2 film

We report measured evolutions of the optical band gap, refractive index and relative dielectric constant of TiO₂ films obtained by electron beam gun evaporation and annealed in an oxygen environment. A negative shift of the flat band voltage with increasing annealing temperatures, for any film thickness, is observed. A dramatic reduction of the leakage current by about four orders of magnitude to 5×10⁻⁶ A cm⁻² (at 1 MV cm⁻¹) after 700°C and 60 min annealing is found for films thinner than 15 nm. The basic carrier transport mechanisms at different ranges of applied voltage such as hopping, space charge limited current and Fowler–Nordheim is established. An equivalent SiO₂ thickness in order of 3.5 nm is demonstrated.     

Optically induced charge storage in ion implanted SiO2

Charge storage in MOS structures with an ion implanted oxide layer has been investigated. The electrons generated by internal photoemission are captured in SiO₂ traps which are created by the implantation of Kr⁺ and N⁺ ions at energies of 50–290 keV and a fluence up to 10¹⁴ cm^?2. The charge storage results in a voltage shift of the high frequency C-V-curve. The dependence of electron storage on exposure time has been measured and compared with approximative calculations. The discharge of traps occurs by heating treatment and hints at the existence of deep oxide traps combined with structural lattice defects.     

Hf-doped Ta2O5 stacks under constant voltage stress

The stress-induced leakage current in Hf-doped Ta₂O₅ layers (7; 10 nm) under constant voltage stress at gate injection was investigated in order to assess the mechanisms of conduction, the traps involved and the effect of Hf doping. The amount of Hf is found to affect the conduction mechanisms, the temperature dependence of the leakage current and the current response to the stress. A significant leakage current increase is observed only when the stress voltage and/or stress time exceed the corresponding threshold values, where the charge trapping at the pre-existing traps dominates below and defect generation above these threshold values. The energy levels of the traps responsible for the current transport are estimated. The stress effect on dominant conduction mechanisms appears quite weak, and the nature of the traps controlling the current transport before and after the stress seems to be nearly identical. The results indicate that the constant voltage stress affects the pre-existing traps in Hf-doped Ta₂O₅ and modifies their parameters, but there is no evidence for stress-induced generation of traps with completely new nature different from oxygen-vacancy related defects.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.     

Electron states at the (1 0 0)Ge/HfO2 Interface

The energy distribution of extended and localized electron states at the Ge/HfO₂ interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO₂ layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO₂ structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO₂ interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO₂ interface traps, approaching ≈1×10¹² cm⁻² eV⁻¹ near the Ge midgap.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.