A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.     

A pair of bipolar memory LSI chips for mainframe computers

A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address access time of 6.7 ns and a typical power dissipation of 3.9 W. It is used in the translation lookaside buffer and the buffer address array of Hitachi's M200H computer to speed up dynamic address translation and buffer storage control. The other chip is a standard 1K bit RAM with a typical address access time of 5.5 ns and a typical power dissipation of 800 mW. It is used in the buffer storage. The primary fabrication process employs oxide isolation with double layer metallization, with minimum line width-plus-spacing of 8 /spl mu/m.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A 0.5-GHz CMOS digital RF memory chip

In the application of digital RF memory (DRFM) chips for radar jamming, an RF signal is sampled, stored in random access memory (RAM) and later recreated from the stored data. A CMOS (l/SUB eff/=1 /spl mu/m) DRFM chip is described that integrates static RAM, control circuitry, and two channels of shift registers on a single chip. The sample rate achieved was 0.5 GHz. VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.     

An ultralow power 8K/spl times/8-bit full CMOS RAM with a six-transistor cell

A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.     

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

A 16 DIP, 64 kbit, static MOS-RAM

A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.     

FEBRIS: a chip for pattern recognition

A chip that performs and evaluates a 16/spl times/16-pixel comparison for application in pattern recognition systems is described. The on-chip data organization and the Wallace-tree evaluation circuits are described. The chip has been realized in a 2-/spl mu/m NMOS process and operated at 18 MHz, thus performing four gigapixel operations per second.     

A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology

A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8/spl times/8 /spl mu/m/SUP 2/, even with relatively conservative 2.0-/spl mu/m design rules, a small die size of 5.69/spl times/5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 /spl mu/s/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.     

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.     

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

A two-phase plasma-coupled static shift register

In designing an experimental 2-bit plasma-coupled shift register, fabricated with standard bipolar technology, it is shown that a simplification of the existing plasma-coupled device (PCD) concept by omission of the double base diode not only decreases the power dissipation and increases the ease of fabrication, but also increases the attractive simplicity of the basic cell. The average power dissipation of the new device is 200 /spl mu/W/bit at a clock frequency of 3 MHz. The bit density is 135 bit/mm/SUP 2/ with 10-/spl mu/m spacing between interconnection lines 10 /spl mu/m in width. A hypothetical layout with dielectric isolation and closer tolerances results in a bit density of 900 bit/mm/SUP 2/ and an estimated power dissipation of 80 /spl mu/W/bit.     

VMOS technology applied to dynamic RAMs

A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 /spl mu/m photolithography, one-transistor cells with a cell size of 150 /spl mu/m/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 /spl mu/m design rules.     

A wide-band current-controlled oscillator using bipolar-JFET technology

A 256K/spl times/1 bit NMOS dynamic RAM, fabricated using conventional n-channel two-layer polysilicon gate technology, is described. The memory cell was laid out in 5.7 /spl mu/m/spl times/12.5 /spl mu/m, and the die measured 4.84 mm/spl times/8.59 mm which can use a standard 300 mil 16 pin DIP. Reduction of the bit line capacitance was accomplished using the second polysilicon layer for the bit line. Through the use of large memory cell capacitance and special device coating techniques, alpha particle immunity was increased. The memory offers a 160 ns typical access time, 350 ns cycle time, and 250 mW active power dissipation.     

Compact NMOS building blocks and a methodology for dedicated digital filter applications

Building blocks for digital filters are discussed. They require 0.7 mm/SUP 2/ or 3 mm/SUP 2/ per pole-zero for a dedicated and a partly programmable realization, respectively. They are realized in 6 /spl mu/m NMOS technology, with 16-bit words and working at bit rates up to 10 Mbit/s. With the exclusion of data conversion, scaling will make them competitive with switched capacitor realizations for 3 /spl mu/m technology, in terms of silicon area and speed. These compact results are achieved due to proper minimization in the design. The experience with the above designs is then generalized into a methodology for custom digital filters. An important concern is a hardware-minimization scheme over all design levels (algorithm, bit-serial architecture, and layout style) with efficient IC implementation and performance in mind. It leads to the possibility of an automated design. The design is supported by computer aided design tools for design verification on all levels, and for file management as well as layout. A formal design of a third-order elliptical wave digital filter demonstrates the concept. The resulting chip area is 1.8 mm/SUP 2/ in 6 /spl mu/m NMOS. The simulated maximum bit rate is 5 MHz (corresponding to 312 kHz sampling rate), with a power consumption of 18 mW.