低能X射线对NMOST的辐照损伤及退火特性

本文研究了NMOS晶体管低能X射线辐照后氧化物陷阱电荷的产生、界面态的性质及空穴陷阱的退火特性等问题。实验结果表明,电离辐照产生的界面态具有施主性和受主性,而氧化物陷阱电荷引起的电压变化在退火过程中,随外加偏置电场极性的不同,表现出可逆性,它对晶体管阈值电压的变化起着决定性的作用。     

施主型界面态引起深亚微米槽栅PMOS特性的退化

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 ,并与受主型界面态的影响进行了对比 .研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且 N型施主界面态密度对器件特性的影响远大于 P型界面态 ,N型施主界面态引起器件特性的退化趋势与 P型受主界面态相似 ,而 P型施主界面态则与 N型受主界面态相似 .沟道杂质浓度不同 ,界面态引起的器件特性的退化则不同     

施主型界面态引起深亚微米槽栅PMOS特性的退化

基于流体动力学能量输运模型,对沟道杂质浓度不同的槽栅和平面PMOSFET中施主型界面态引起的器件特性的退化进行了研究,并与受主型界面态的影响进行了对比.研究结果表明同样浓度的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件,且N型施主界面态密度对器件特性的影响远大于P型界面态,N型施主界面态引起器件特性的退化趋势与P型受主界面态相似,而P型施主界面态则与N型受主界面态相似.沟道杂质浓度不同,界面态引起的器件特性的退化则不同.     

存在界面陷阱的n沟6H-SiC MOSFET温度特性研究

利用二维器件仿真软件 MEDICI建立了具有指数分布界面陷阱的 n沟 6H-Si C场效应晶体管的结构模型和物理模型 ,通过模拟研究 ,分析和讨论了界面陷阱对器件阈值电压、跨导及其温度特性的影响。     

不同结构nMOS管的总剂量辐射效应北大核心CSCD

X射线直接成像的CMOS图像传感器由于工作在X射线辐射下,其内部器件会因为辐射效应引起性能恶化,因此需要对器件进行抗辐射加固并研究辐射对器件参数的影响。辐射导致的氧化物陷阱电荷及界面陷阱电荷受到栅氧厚度、偏置电压大小、辐射总剂量以及剂量率等多种因素影响。设计了n型场效应晶体管辐射加固结构版图,用0.5μm CMOS工艺流片,并进行了30 kGy(Si)的总剂量辐照效应实验。实验结果显示,所设计的n型场效应晶体管在辐射之后漏电流有所增加、跨导减小、阈值电压向负向漂移;辐射加固晶体管在漏电流性能上较未加固晶体管更好,在跨导改变和阈值电压漂移上未能表现出其更优的性能。     

不同结构nMOS管的总剂量辐射效应

X射线直接成像的CMOS图像传感器由于工作在X射线辐射下,其内部器件会因为辐射效应引起性能恶化,因此需要对器件进行抗辐射加固并研究辐射对器件参数的影响。辐射导致的氧化物陷阱电荷及界面陷阱电荷受到栅氧厚度、偏置电压大小、辐射总剂量以及剂量率等多种因素影响。设计了n型场效应晶体管辐射加固结构版图,用0.5μm CMOS工艺流片,并进行了30 kGy(Si)的总剂量辐照效应实验。实验结果显示,所设计的n型场效应晶体管在辐射之后漏电流有所增加、跨导减小、阈值电压向负向漂移;辐射加固晶体管在漏电流性能上较未加固晶体管更好,在跨导改变和阈值电压漂移上未能表现出其更优的性能。     

注氧SOI上制作的CMOS器件的总剂量特性分析

研究了用注入掩埋氧化物的绝缘体上的硅(SOI)作衬底、并经不同的注入后退火处理而制作的CMOS器件的总剂量特性。所测量到的正面沟道SOI/CMOS器件的阈值电压漂移、亚阈值电压斜率衰减和迁移率衰减情况,与采用相同办法制作的体器件的这些参数的变化情况是一样的。 只要不影响正沟道晶体管性能,加负衬偏可降低背面沟道的阈值电压漂移。在目前采用的工艺条件下,正沟道器件的辐照性能与注入氧后的退火温度无关。辐照时,在硅/隐埋氧化物界面上氧的沉积会促进背沟器件界面态的产生。     

单界面陷阱对7 nm P型GAAFET性能影响研究

采用3D TCAD软件仿真分析了单界面陷阱对7 nm P型全环栅场效应晶体管DC和AC性能的影响。研究结果表明:单个陷阱能使转移特性曲线发生严重偏移;当单界面陷阱位于沟道中心附近且陷阱能级靠近导带时,对关态电流和阈值电压的影响最大;陷阱使栅电容的相对变化量小于1%;环栅晶体管沟道长度和纳米线直径的缩小会加重陷阱对器件性能的影响,高介电常数材料的Spacer可减小陷阱引起的沟道能带弯曲程度,从而缓解陷阱对器件性能的影响。在调节器件结构参数使器件性能最大化的同时,应使陷阱对器件性能的影响最小化。     

22 nm体硅nFinFET总剂量辐射效应研究

通过^(60)Coγ射线辐照试验,研究了22 nm工艺体硅nFinFET的总剂量辐射效应,获得了总剂量辐射损伤随辐照偏置和器件结构的变化规律及损伤机理。研究结果表明,经过开态(ON)偏置辐照后器件阈值电压正向漂移,而传输态(TG)和关态(OFF)偏置辐照后器件阈值电压负向漂移;鳍数较少的器件阈值电压退化程度较大。通过分析陷阱电荷作用过程,揭示了产生上述试验现象的原因。     

电子、质子、X和Y射线辐照过程中和辐照后加固MOS器件的损伤恢复

本文报导了电子、质子、X和Y射线辐照期间和辐照后加固MOS器件的恢复特怀。结果表明,复杂的恢复特性受被试元件的损伤灵敏度控制。结果还表明,损伤灵敏度取决于剂量率、总剂量、电源偏置、栅极偏置、晶体管类型、辐射源和粒子能量。如果没有相应的地面的试验和分析结果,这些依赖关系的复杂性质来解释在空间(暴露在电子和质子的整个光谱中)的LIS器件即或不是不可能的。性能也是十分困难的。某些情况下,n沟器件的阈值电压漂移可以在辐照后几小时之内完全恢复,这时具有的阈值电压平衡值大于辐照前的值。这个效应取决于总剂量,辐射源和暴露过程中的栅偏置电压。相比之下,p沟器件的阈值电压漂移在受辐射后30天内只能恢复20％。     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Damage to insulated gate FETs by electron beam metrology and X-ray exposure

A comparison of the damage induced by X-rays and electron-beam radiation on IGFETs has been made. It is observed that the ratio of the threshold voltage shift due to fixed positive charge (ΔV _FPC) to the total threshold voltage shift (due to both fixed positive charge and neutral electron traps) does not show any dependence on the radiation dose in the case of an E-beam irradiation, and shows a negative slope for X-ray irradiated samples. This suggests that the amount of neutral electron traps (NETs) and fixed negative charge (FNC) produced by the ionizing radiation is higher in the case of X-ray irradiation and saturates at much higher doses compared to E-beam irradiation. A study of electron beam damage at various energies shows that E-beam energy of 7 keV does not damage the oxides at all whereas at lOkeV maximum damage is observed. For devices exposed to X-rays, the threshold voltage shift ratios due to the fixed positive charge for different gate oxide thicknesses (12·6nm-50·0nm) indicate a shift of the effective charge centre-id which also depends on the filling of neutral electron traps to form fixed negative charges that partially compensate the fixed positive charges. The threshold voltage shift ratios also indicate a shift in the charge centroid which is pronounced in the thinner oxides. A model for the change in effective centroid of charge and also its dose dependence for different oxide thicknesses has been suggested.     

Hot-electron-induced traps studied through the random telegraphnoise

Random telegraph signal (RTS) measurements have been used to study individual hot-carrier-induced traps in nMOSFETs. It is shown that single filling and emptying can cause 0.1% step noise in channel current. Trap location (3-10 A from interface), time constant (~10 ms), and energy are found to be quite different from those of prestress (process-induced) traps. The type (acceptor or donor) of the traps can also be identified by RTS measurements; both the process and stress-induced traps with energies near the conduction band edge are found to be of the acceptor type for nMOSFETs and trap levels near the valence band edge are found to be of the donor type for pMOSFETs. Using RTS as a characterization tool, it is found that the stress-induced interface traps are located closer to the interface, resulting in shorter time constants and a stronger influence on the surface mobility than the process-induced traps     

三栅FET的总剂量辐射效应研究

通过对赝MOS进行不同剂量的辐射,得到不同辐射条件下赝MOS器件的I-V特性曲线,并通过中带电压法进行分析,得出在不同辐射下SOI材料的埋氧层中产生的陷阱电荷密度和界面态电荷密度参数。采用这些参数并结合Altal三维器件模拟软件模拟了硅鳍(FIN)宽度不同的三栅FET器件的总剂量辐射效应,分析陷阱电荷在埋氧层的积累和鳍宽对器件电学特性的影响。     

雪崩热电子注入研究富氮SiO_xN_y纳米级薄膜的陷阱特性

采用雪崩热电子注入技术研究了富氮 Si Ox Ny 纳米级薄膜的陷阱特性。观察到该薄膜存在着受主型电子陷阱 ,随着注入的增长、界面上产生的这种陷阱将起主导作用 ,其密度大过施主型界面电子陷阱。揭示出界面陷阱密度在禁带中分布 ,其密度随雪崩注入剂量增加而增大 ,禁带上半部增大得尤其显著。指出雪崩注入过程中在 Si/ PECVD Si Ox Ny 界面上产生两种性质不同的电子陷阱 ,并给出它们在禁带中的位置及密度大小关系。支持了界面陷阱来源于悬挂键的物理模型 ,由于本实验的重要结果可用该理论模型圆满地解析。给出 PECVD形成纳米级薄膜的优化工艺条件 ,该条件成膜的界面特性良好、耐压范围高、抗雪崩注入能力及其他电子特性也较好     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

Detailed investigation of n-channel enhancement 6H-SiC MOSFETs

Basic MOSFET parameters like inversion layer mobility, threshold voltage, intrinsic mobility reduction factor and interface state density extracted from the subthreshold slope were examined in detail for 6H-SiC enhancement-mode n-channel MOSFETs. The inversion layer mobility and the threshold voltage were determined as a function of substrate doping concentration as well as device temperature. The interface state density was studied for different substrate doping concentrations. The inversion layer mobility was found to decrease strongly with increasing substrate doping. In contrast to earlier reports the inversion layer mobility decreases also with temperature. Furthermore, the threshold voltage depends more pronounced on substrate doping and temperature than theoretically expected. The interface state density extracted from the subthreshold slope increases significantly with substrate doping concentration. All these phenomena are consistently interpreted by the classical MOSFET behavior which is extended by acceptor like interface states. These states are located close to the conduction band and exhibit a density increasing drastically toward the band edge     

PMOS剂量计的稳定性研究

在室温条件下 ,研究了辐照偏置、总剂量和剂量率对 PMOS剂量计辐照剂量记录 -阈电压的稳定性影响 ,观察了辐照后阈电压在不同栅偏条件下的变化趋势和幅度。分析认为慢界面陷阱中电荷的“充放电”是造成不稳定的首要原因。结果表明 ,该种由慢界面态造成的阈电压变化在每次开机测量下具有重复性。讨论了在 PMOS剂量计中提高稳定性的办法。