Subnanosecond emitter-coupled logic gate circuit using Isoplanar II

Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.     

A flexible approach to emitter-coupled logic arrays

The ECCSL arrays have been successfully fabricated using two levels of metalization on 120 by 120-mil chips. The yield, fabrication, and performance studies of these arrays, while not yet complete, indicate that current mode logic arrays of 10 to 30 gates are entirely feasible. This is especially true if the size of the chips are reduced as much as possible (preferably below 0.10 by 0.10 inch.) Indications are that arrays with relatively low gate counts (10 to 30 gates) greatly reduce the testing problems usually associated with array technology.     

Transferred-electron logic gates

A two-dimensional modeling technique is used to simulate GaAs transferred-electron devices operated as a logic gate (the TELD) and as a threshold gate. The simple logic gate has a good transfer characteristic but is shown sensitive to bias variations and operates with monostable output. For an input logic swing of 0.6 V and a fanout of 2, a propagation delay of 26 ps and gain of 1.25 is predicted. A bi-stable threshold gate shows a turn-on time of about 80 ps. An FET-triggered two-terminal transferred-electron device is calculated to have propagation delay of 27 ps with a gain of -1.2. Subsequent similar stages would require a noninverted output obtainable from a capacitive electrode on the TED. However, it is shown that additional anode load resistance is required to obtain a significant positive pulse output from such capacitive electrodes. The bias power requirement is estimated to be similar to the simple TELD gate.     

A four-variable programmable universal logic module using digital summation threshold logic gates

Combining the concepts of programmable logic arrays (PLAs) and conventional universal logic modules (ULMs) a new type of programmable ULM for four variables has been proposed. The realization is based on the digital summation threshold logic (DSTL) gates, a cellular array for realizing threshold logic functions.     

Fully-compensated emitter-coupled logic: Eliminating the drawbacks of conventional ECL

New approaches to high-speed emitter-coupled logic circuitry, overcoming system drawbacks by eliminating sensitivity to environmental changes, are discussed. A comparison is made with uncompensated conventional ECL. Circuits displaying threshold and level invariance over wide ranges of ambient temperature, typically greater than 0/spl deg/-75/spl deg/C, and supply voltage, -4.7 to -6.2 V, are described. Suggestions are made as to how these features can lead to higher performance, and at the same time, lower cost systems.     

Spatial soliton all-optical logic gates

We demonstrate some basic all-optical (electrically unbiased) logic gates in azobenzene liquid crystalline cells, exploiting their large nonlinearity for light localization and the trans-cis photoisomerization for all-optical external control. Spatial solitons were excited at microwatt power levels at 632.8 nm, whereas gating and switching were achieved with milliwatt beams at 409 nm.     

Complementary GaAs MESFET logic gates

Operation of the first complementary GaAs MESFET (CMES) logic gates is reported. Direct-coupled inverters utilizing p- and n-channel ion-implanted MESFET's demonstrate good transfer characteristics with less than 5-µW power dissipation per gate. Propagation delays as small as 54 ps are attained in 13-stage ring oscillators at room temperature with speed-power products as small as 6 fJ.     

Femtojoule Josephson tunneling logic gates

The design of Josephson tunneling logic (JTL) gates capable of performing the logic functions of AND, OR, INVERT and CARRY is considered. The design equations were solved for a rectangular Josephson junction in which the geometry was adjusted to ensure that all logical inputs were equivalent. Experimental JTL gates were found to operate with a logic delay of less than 200 ps, and with a power-delay product of the order of five femtojoules.     

Shunt-feedback Schottky clamped logic gates

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.     

All-optical tree-based greedy router using optical logic gates and optical flip-flops

Due to ever-increasing throughput demands, the lookup in conventional IP routers based on longest prefix matching is becoming a bottleneck. Additionally, the scalability of current routing protocols is limited by the size of the routing tables. Geometric greedy routing is an alternative to IP routing which replaces longest prefix matching with a simple calculation employing only local information for packet forwarding. For the first time, in this paper we propose a novel and truly all-optical geometric greedy router based on optical logic gates and optical flip-flops. The circuit of the router is constructed through the interconnection of SOAs and directional couplers. The successful functionality of the proposed router is verified through simulation. The circuit enables high data rate throughput.     

Computer modelling of bipolar logic gates

A basic approach to the computer modelling of large arrays of bipolar gates using continuous analytic expressions is presented. A program has been written which applies this principle. It can handle complex situations and is justified on grounds of efficiency with l.s.i. circuits.     

Frequency-tunable logic gates in graphene nano-waveguides

In this study, simple basic plasmonic logic gates of XOR, OR, and NOT based on graphene nano-ribbon resonators coupled to properly designed arrangements of nano-waveguides, as input and output logic ports, are demonstrated. The operation of the structures as frequency selective components is based on the propagation of edge modes in nano-waveguides and coupling to nano-ribbon resonators located in appropriate locations. The gates performance is investigated through analytic approaches and verified numerically using the finite difference time domain method. Typical extinction ratio of about 8 dB between ON and OFF logic states has been attained. According to the fantastic feature of voltage-dependent chemical potential of graphene conductivity, the characteristics of the structures can be actively manipulated. These sub-wavelength plasmonic components can be employed extensively in terahertz demanded applications.

     

Voltage-controlled oscillator using an emitter-coupled differential pair

A voltage-controlled oscillator using the antisymmetric transfer characteristics of an emitter-coupled differential pair of transistors is presented. Variation of the differential bias condition of this pair changes the average slope of Its transconductance parameter, thereby changing the frequency of the near harmonic mode of oscillation in a system which has been shown to produce van-der-Pol-type oscillations with passive parameter control only. Over a sufficiently wide range of frequency the distortion of this oscillation is reasonably low. A simple slope/differential-voltage relation is proposed to calculate the frequencies by computer solution of the general relation, as well as by approximate solution by using the method of small parameters. Experimental results are also presented for comparison.     

Optical parallel logic gates using a shadow-casting system for optical digital computing

A new, simple method of optically implementing optical parallel logic gates has been described. Optical parallel logic gates can be implemented by using a lensless shadow-casting system with a light-emitting diode (LED) array as a light source. Pattern logic, i.e., parallel logic for two binary patterns (variables), is simply obtained with these gates; this logic describes a complete set of logical operations on a large array of binary variables in parallel. Coding methods for input images are considered. Applications of the method for a parallel shift operation and optical digital image processing, processing of gray-level images, and parallel operations of addition and subtraction for two binary variables are presented. Comparison of the operation of the proposed optical logic gate with that of array logic in digital electronics leads to a design concept for an optical parallel array logic system available for optical parallel digital computing.     

Rise time of emitter-coupled logic circuits including the effects of collector-to-base capacitances

Rise times of emitter-coupled logic circuits are computed, taking into account collector-to-base capacitances as well as gain-bandwidth products, ohmic base resistances, external stray capacitances, and the finite rise time of the input signal. Basic considerations are discussed, and explicit expressions and graphs are given for a wide range of circuit parameters.     

Efficient realisation of MOS-NDR threshold logic gates

A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.     

Minimum-width control-current pulse for Josephson logic gates

For a given level of overdrive, there exists a minimum-width control-current pulse that must be applied to switch a Josephson logic gate. Determination of this minimum pulsewidth is useful in setting limits on the speed of various Josephson circuit configurations and also in finding the narrowest pulse that a Josephson-junction gate can detect when it is employed as a pulse detector. The minimum control-current pulsewidth is a strong function of the overdrive factor of the control current. It scales as(C/I_{m})^{1/2}, where Imis the junction critical current, andCis the capacitance, and is on the order of 10 ps for Josephson quantum interferometers in 5-µm technology. Computer simulations have been done to find the dependence of minimum control-current pulsewidths on overdrive magnitude for a single-junction gate and for two- and three-junction interferometers. Analytic expressions of the minimum control-current pulsewidth that are in good agreement with simulations have been obtained for these three types of Josephson logic gates.     

Ultra-low-power carbon nanotube FET-based quaternary logic gates

This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.