A 2-GHz CMOS image-reject receiver with LMS calibration

This paper describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-/spl mu/m CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and a third-order input intercept point of -17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 /spl times/ 1.84 mm/sup 2/.     

A CMOS Monolithic Image-Reject Filter

A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two -enhancement techniques are utilized to circumvent the low characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 m CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and –20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.     

A 2-V, 2-GHz low-power direct digital frequency synthesizerchip-set for wireless communication

A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which synthesizes a sine wave at 55 Msps with an internal 10 b digital-to-analog converter (DAC) and Si bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. Operation of 2 V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz     

A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply

We report an ultra-low-voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm. The 3.4 mm² chip consumes 8.5 mW from a 0.5 V supply.     

A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection

A fully integrated Global Positioning System (GPS) radio is presented. Low-IF architecture was used for a high level of integration and low power consumption. An on-chip analog image-reject filter provides 18 dB of image-noise rejection to prevent noise figure (NF) degradation. With image rejection performed in the analog radio, a single-path (nonquadrature) output was used. The integrated synthesizer only requires an off-chip phase-locked loop-filter to function. Implemented in a 0.35-/spl mu/m 2P4M CMOS process, the integrated radio has a chip area of 9.5 mm/sup 2/. The radio operates over a wide range of voltage and temperature, from 2.2 to 3.6 V and from -40/spl deg/C to +85/spl deg/C and consumes 27 mW from a 2.2-V supply. The receiver has 4 dB NF.     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

CMOS mixers and polyphase filters for large image rejection

This paper presents an in-depth treatment of mixers and polyphase filters, and how they are used in rejecting the image in transmitters and receivers. A powerful phasor-based analysis is used to explain all common image-reject topologies and their limitations, and it is shown how this can replace complex trigonometric equations commonly found in the literature. Practical problems in design and layout that limit the performance of image-reject upconversion and downconversion mixers are identified, and solutions are presented or limits explained. This understanding is put to work in a low-IF CMOS wideband, low-IF downconversion circuit, which repeatedly rejects the image by 60 dB over the wide band of 3.5 to 20 MHz without trimming or calibration     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 Ω) when operating from a 0.9 V supply     

Macromodels in the frequency domain analysis of microwave resonators

This paper describes a 1-V operation Bluetooth RF transceiver in 0.2-/spl mu/m CMOS SOI. The transceiver integrates a radio-frequency transmit/receive switch, an image-reject mixer, a quadrature demodulator, g/sub m/-C filters, an LC-tank voltage-controlled oscillator, a phase-locked loop synthesizer, and a power amplifier. The phase shifter in the quadrature demodulator is tuned dynamically to track the carrier-frequency drift allowed in the Bluetooth specification. The g/sub m/ cell in the filters uses depletion-mode pMOS transistors. In order to achieve 1-V operation, LC-tuned-folded and transistor-current-source-folded circuits are used in the RF and IF building blocks, respectively. In order to minimize power consumption, the current flowing through the circuit is optimally shared between the folded stages. A tuning circuit for the g/sub m/-C filters and a bias generation circuit ensure stable transceiver performance. The transceiver shows -77-dBm sensitivity at 0.1% bit error rate and consumes 33 and 53 mW from 1 V in the transmit and receive modes, respectively.     

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm² in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW     

A fully integrated SONET OC-48 transceiver in standard CMOS

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-μm CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps     

Low sensitivity complex image rejection filter for GNSS receivers

In this paper, a new approach for the design of a low sensitivity complex-filter is proposed. The approach is based on realising the filter using low sensitivity allpass sections. The complex filter obtained can be used as image-reject filter in low-IF GNSS receivers. The filter configuration is modular, i.e. is composed of the same subcircuits which simplifies the design of the circuit. A Chebyshev type OTA-C image-reject filter obtained by cascading two third-order allpass-based complex filters is presented. Post layout simulation results of the filter using SPECTRE in CADENCE design tool verifying its proper operation are provided.     

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS

The design and measurement of two optical receivers with integrated photodiode in 130 nm CMOS is presented. The low bandwidth, which is typical for photodiodes in CMOS technologies, is circumvented by a differential photodiode topology on the one hand and by including an optimized equalizer in the receiver chain on the other hand. The low responsivity of a CMOS photodiode is compensated by a very low-noise design for the differential TIA. The disadvantage of such a low-noise design is its high power consumption. Therefore, a design strategy is presented where part of the circuit is biased in weak inversion. Doing so, the power consumption is decreased from 138 mW for the standard design to only 74.16 mW. Both designs are measured optically with 850 nm modulated light and are able to operate at 4.5 Gbit/s with a BER lower than 10^-12. The sensitivities for this BER and speed are - 3.8 dBm and -3.4 dBm respectively. The receivers even work up to 5 Gbit/s for BER values around 10^-9.     

CMOS equaliser for compensating sinc(x) distortion of video D/Aconverters

The authors describe the design and CMOS realisation of a new g _m-C amplitude equaliser for correcting sinc(x) distortion in video D/A converters. Simulated and measured results demonstrate how the equaliser is used to correct distortion in D/A converters with F_s =13.5 MHz to ⩽0.08 dB ripple over 5 MHz bandwidth. Fabricated using a 0.8 μm CMOS process, the equaliser occupies 0.7 mm² and dissipates 20 mW from a 5 V supply     

A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescalerusing a divide-by-2/3 synchronous counter

An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler that operates at up to 1 GHz and dissipates 0.9 mW at a supply voltage of 1 V is presented. The prescaler is capable of 2-GHz performance with dissipation of 7.2 mW at 2 V. This superior performance is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX process technology combined with a circuit configuration that uses a divide-by-2/3 synchronous counter. Using these same technologies, a single-chip CMOS phase-locked-loop (PLL) LSI that uses the developed prescaler was fabricated. It can operate at up to 2 GHz while dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower supply voltage of 1.2 V, 1-GHz operation can be obtained with a corresponding power consumption of 1.4 mW. These results indicate that the high-speed and very-low-power features of CMOS/SIMOX technology could have an important impact on the development of future personal communication systems     

Ultra low power 2.4-GHz 0.35-/spl mu/m CMOS dual-modulus prescaler design

This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-/spl mu/m standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications

This paper presents a novel CMOS impulse radio (IR) ultra-wide-band (UWB) transceiver system design for future contact-less chip testing applications using inductive magnetic coupling as wireless interconnect. The proposed architecture is composed of a simple and robust design of a Gaussian monocycle impulse generator at the transmitter, a wideband short-range on-chip transformer for data transmission, and a g_m-boosted common-gate low-noise amplifier in the UWB receiver path. SpectreRF post-layout simulation with a 90-nm CMOS technology shows that the transceiver operates up to a 5 Gb/s data rate, and consumes a total of 9 mW under a 1-V power supply.