A Systematical Approach for Noise in CMOS LNA

A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5.2GHz CMOS LNA.     

一种新颖的低噪声放大器的噪声优化方法

This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.     

A 20MHz Low Phase-Noise 0.35μm CMOS Crystal Oscillator

The design procedure of a CMOS process integrating Colpitts crystal oscillator is described in detail by using the tools of Matlab and advanced design system (ADS). The small-signal analysis is performed both in the viewpoint of negative resistance and positive feedback. The analysis of condition for reliable start-up of oscillation and design guides for low phase noise is introduced The measured phase noise is -172dBc/Hz@10 kHz and the power dissipation is 0.36 mW at power supply 3 V.     

ANALYSIS OF INTERNALLY GENERATED NOISE OF BIOELECTRIC AMPLIFIERS

This papenr deals with internally generated noise of bioelectric amplifiers that are usually used for processing of bioelectric events.The main purpose of this paper is to present a procedure for analysis of the effects of internal noise generated by the active circuits and to evaluate the output noise of the author‘s new designed bioelectric amplifier that caused by internal effects to the amplifier circuit itself in order to compare it with the noise generated by conventional amplifiers.The obtained analysis results of internally generated noise showed that the total output noise of bioelectric active circuits does not increase when some of their resitors have a larger value.This behavior is caused by the different transfer functions for the signal and the respective noise sources associated with these resistors.Moreover,the new designed bioelectric amplifier haws an output noise less than that for conventional amplifiers.The obtained analysis results were also experimentally verified and the final conclusions were drawn.     

Design and simulation of optoelectronic oscillator with micro ring resonator and radio frequency amplifier modelling at 110 GHz

There is an increasing need for high performance oscillators as the faster transmission networks demand for high frequency signals. Opto-electronic oscillators (OEO) enable us to make better oscillators in terms of size, weight and power. In this paper, photonic integration is proposed for realizing the OEO with micro ring resonator (MRR) and radio-frequency (RF) amplifiers of monolithic microwave integrated circuit (MMIC), which can be used for generating 110 GHz sine wave. The OEO architecture is proposed and block diagram developed considering Silicon based MRR and three-stage RF amplifier based on GaN high-electron-mobility transistor (HEMT). A simulation model is developed according to the Klein model of MRR and is validated against the calculated performance parameters. MRR dimensions are calculated as with silicon on insulator (SOI) technology and a radius 5.27 μm for the device is derived. Free spectral range (FSR) of 48.52 nm and filter rejection ratio of 16.79 dB are obtained for this device. The proposed RF amplifier is modelled with GaN parameters derived from high frequency pinch-off model and with power amplifier considerations. The gain for this amplifier is obtained as 10.6 dB. The OEO design is developed in this project in such a way that the system can be manufactured with the existing methods.     

S-band low noise amplifier using 1μm InGaAs/InAlAs/InP pHEMT

正This paper discusses the design of a wideband low noise amplifier(LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications.The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT.Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz.A common-drain in cascade with a common source inductive degeneration,broadband LNA topology is proposed for wideband applications.The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss(S_(11)—10 dB,S_(22)—11 dB).This LNA exhibits an input 1-dB compression point of-18 dBm,a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

Constraint Symbolization Method for Analog Layout Retargeting with Geometric Programming

To satisfy the requirements of complex and special analog layout constraints, a constraint symboliza- tion method based on geometric programming for analog layout retargeting is presented in this paper. Our ap- proach is to build symbolic template for layouts, then uses Geometric programming （GP） to achieve new technology design rules, implement device symmetry and matching constraints, and manage parasitics optimization. The GP, a class of non-linear optimization problem, can be trans- ferred or fitted into a convex optimization problem. There- fore, a global optimum solution can be achieved. The sym- bolization method ensures the layout retargeting automati- cally. The efficiency and effectiveness of the proposed algo- rithm, as compared with the other existing methods, are demonstrated by a basic case-study example and a two- stage Miller-compensated operational amplifier.     

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed.The relevant parameter analysis and the details of circuit design are presented.The test chip was implemented in a TSMC 0.18μm 1P4M RF CMOS process.The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz.The measured noise figure is around 1.5-1.7 dB on both bands.The LNA consumes less than 4.3 mA of current ...     

电流模线性控制电荷泵的研究与设计

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.     

Ka频段低噪声放大器的设计

介绍了Ka频段低噪声放大器的设计方法，采用HP－EESOF公司Libra软件对有源器件进行直流分析与参数提取，并运用小信号线性分析法进行电路模拟与设计。研制的放大器在34－36GHz频率下噪声系数小于3dB。     

运算放大器的低频噪声测试方法

运算放大器广泛应用于电路设计中,其可靠性指标直接影响电路系统的性能.运放器件的低频噪声特征同其性能及可靠性指标密切相关.本文中详细给出了运放器件低频噪声的测试方法并对测试过程中的若干关键问题进行了深入剖析.     

5~6 GHz限幅低噪声放大器的研制

采用GaAs增强型pHEMT工艺,将限幅器和低噪声放大器集成在同一衬底,设计了一款用于5~6 GHz的限幅低噪声放大器。限幅器采用PIN二极管进行设计,低噪声放大器采用并联负反馈、源级电感负反馈以及电流复用结构,减小功耗的同时改善了增益平坦度和稳定性。测试结果表明,在工作频带内,限幅低噪声放大器的增益为27±0.2 dB,噪声系数为1.1~1.3 dB,总功耗为240 mW,耐功率大于46 dBm(2 ms脉宽,30%占空比),芯片尺寸为3.3 mm×1.3 mm。     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

CMOS运算放大器的设计与Cadence仿真

本文根据运算放大器的设计要求(开环电压增益、相位裕度),分析了CMOS运算放大器的性能参数,设计出器件的几何尺寸,最后通过Cadence仿真得到性能指标的仿真结果.     

GaAs cryo-cooled LNA for C-band radioastronomy applications

The design procedure and measurements of a C-band high-performance GaAs cryo-cooled low noise amplifier (LNA) are presented. The latter provides 30 dB gain, a noise figure (NF) lower than 0.12 dB (i.e. 8 K equivalent noise temperature) at 25 K operating temperature, with 35 mW DC bias power only. An appropriate scaling of the device gate periphery has been adopted to trade-off the LNA's NF and DC power consumption.     

一种兼顾速度和功率损耗的硅探测器模拟前端电路设计

提出了一种兼顾速度和功率损耗的增益可调模拟前端电路,适用于硅探测器。该电路主要由快速电荷灵敏放大器、整形器以及可调节主要参数的控制系统组成。其中快速电荷灵敏放大器由低噪音场效晶体管（JFET）和电流反馈运算放大器构成,以确保较高频率和较短上升时间。整形器为五阶复数滤波器,能够提供较高的对称脉冲。通过实验验证了其可行性,在电容小于100 pF的范围内,实现了6种可调增益且兼顾了速度和功率损耗,电荷灵敏放大器上升时间为12ns,功率损耗为96mW。当探测器电容为40 pF时,等效噪音电荷（ENC）均值为180e-。     

集成运算放大器同相和反相形式的E_n-I_n噪声分析和比较

本文通过分析和比较同相和反相放大器E_n-I_n噪声的特点,给出了若干新结果。本文方法在低噪声运放电路设计和运放噪声参数提取中都具有十分重要的意义。     

High-performance in W-band monolithic pseudomorphic InGaAsHEMT LNA's and design/analysis methodology

High-performance W-band monolithic one- and two-stage low noise amplifiers (LNAs) based on pseudomorphic InGaAs-GaAs HEMT devices have been developed. The one-stage amplifier has a measured noise figure of 5.1 dB with an associated gain of 7 dB from 92 to 95 GHz, and the two-stage amplifier has a measured small signal gain of 13.3 dB at 94 GHz and 17 dB at 89 GHz with a noise figure of 5.5 dB from 91 to 95 GHz. An eight-stage LNA built by cascading four of these monolithic two-stage LNA chips demonstrates 49 dB gain and 6.5 dB noise figure at 94 GHz. A rigorous analysis procedure was incorporated in the design, including accurate active device modeling and full-wave EM analysis of passive structures. The first pass success of these LNA chip designs indicates the importance of a rigorous design/analysis methodology in millimeter-wave monolithic IC development