基于SIFT特征和误匹配逐次去除的图像拼接

针对随机抽样一致性算法(RANSAC)计算量大、耗时长、匹配点选取不当会影响变换矩阵精度、阈值的鲁棒性较差,以及不能完全去除误匹配等不足,提出了一种基于SIFT特征和误匹配逐次去除的图像拼接算法.该算法首先提取图像的SIFT特征,并利用近似的最近邻搜索算法(BBF)进行特征初始匹配,然后利用一种误匹配逐次去除的迭代算法正确地估计图像间的变换矩阵.在这种误匹配逐次去除的迭代算法中,采用预检测模型的方法,减少了迭代运算的数据量,提高了拼接速度;采用匹配点按块随机选取的方法保证了变换矩阵的稳定性和精确度;通过逐次筛选去除误匹配,且在筛选过程中采用自适应阈值,完全去除了误匹配.实验结果表明,该算法在保证较高精度和鲁棒性的情况下,缩短了拼接时间,提高了拼接效率.     

BCH-Turbo码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案.本方案采用BCH码作为Turbo迭代译码的停止准则,并对每一个分量译码器结果都进行判断,可提前停止迭代.通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低,Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降.本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响.     

针对极化码置信度传播算法的低复杂度早期停止准则

针对极化码译码延迟较高的问题,该文提出了一种针对置信度传播算法的早期停止准则,通过监测码字估值(x)的收敛性来终止译码.该准则利用高斯近似分析选取码字中Q个出错概率较小的比特构成比较空间,由于比较的位数较少,且仅采用异或和或运算,其计算复杂度较低.与基于信息序列估值(u)的方案不同,提出的准则在计算(u)之前已完成检测,不会导致额外的译码延迟.仿真和FPGA综合结果表明:该准则相对于G-Matrix,最坏信息位(WIB)和冻结位误码率(FBER)可有效节省硬件资源;当最大迭代次数设置为40次时,相比于G-Matrix准则,复杂度下降的代价是平均迭代次数在3.5 dB处上升了29.98％,相比于WIB和FBER方案,平均迭代次数分别减少39.44％和27.67％.     

基于Gold序列的相干OCDMA系统性能分析

随着相位编解码器关键技术的突破,相干光码分多址(OCDMA)系统也受到更多关注.采用前向纠错(BCH)信道编码技术,分析了相位编码光码分多址系统误比特率的计算方法,定义了相干OCDMA系统的频谱效率,讨论了系统端到端误比特率和平均丢包率的计算及其影响因素.得到使用BCH信道编码可以降低系统的误比特率和提高系统频谱效率的结论,并证明相位编码OCDMA系统适合传输变长数据包,网络中节点数目的增加对其误比特率影响不大.     

CCD像元尺寸对傅里叶变换法相位测量精度的影响

针对随机抽样一致性算法(RANSAC)计算量大、耗时长、匹配点选取不当会影响变换矩阵精度、阈值的鲁棒性较差, 以及不能完全去除误匹配等不足, 提出了一种基于SIFT特征和误匹配逐次去除的图像拼接算法。该算法首先提取图像的SIFT特征, 并利用近似的最近邻搜索算法(BBF)进行特征初始匹配, 然后利用一种误匹配逐次去除的迭代算法正确地估计图像间的变换矩阵。在这种误匹配逐次去除的迭代算法中, 采用预检测模型的方法, 减少了迭代运算的数据量, 提高了拼接速度; 采用匹配点按块随机选取的方法保证了变换矩阵的稳定性和精确度; 通过逐次筛选去除误匹配, 且在筛选过程中采用自适应阈值, 完全去除了误匹配。实验结果表明, 该算法在保证较高精度和鲁棒性的情况下, 缩短了拼接时间, 提高了拼接效率。     

一种级联的Turbo码系统

利用RS码和Turbo码级联,产生了一种级联的Turbo码系统。通过仿真,发现该系统具有较好的误帧率(FER),并且对AWGN信道中高信嗓比下的“平板效应”也有一定的抑制作用。同时,通过特定的动态终止算法,可以减少Tur-bo码译码的迭代次数,节省译码时间。     

一种低复杂度LDPC码提前结束迭代准则

采用直接观察校验子S中非零元素个数的方法来确定LDPC译码器迭代译码的收敛情况,提出了一种低复杂度的提前结束迭代准则.在不需要经过复杂的计算便可确定迭代译码的收敛情况,从而可以根据系统的实际需要实现性能和平均迭代次数的折衷.在CMMB标准下,对800×9 216个LDPC码字仿真表明该准则能在很小的性能损失的情况下很大程度地降低平均迭代次数.与现有的几种经典的提前结束迭代准则相比该准则具有性能良好、低复杂度和硬件消耗少的特点.     

BCH-Turbo编码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案。本方案采用BCH码作为Turbo迭代译码的停止准则。并对每一个分量译码器结果都进行判断。可提前停止迭代。通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低。Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降。本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响。     

分组相关快衰落信道下自适应Turbo码译码算法研究

分析了分组相关快衰落信道的特性，推导出该信道下Turbo码译码算法；研究了迭代次数对Turbo编码系统的影响，在小信噪比弥散度条件下，提出基于平均信噪比的最佳迭代译码次数自适应选择方案，可以兼顾译码性能和译码速度，得到较低的平均误比特率和较高的平均译码速度。仿真结果说明，本文提出的Turbo码译码算法，降低了对信道估计精度要求的同时，得到精确信道估计时的性能；对于目标误比特率为10^-4时，采用自适应Turbo译码算法，与固定迭代4次相比，平均误比特率降低了40％，提高了系统性能；而与固定迭代8次相比，迭代次数降低了约1／4，提高了译码速度。     

基于伴随向量和的软值翻转LDPC译码算法

通过分析置信传播译码算法失败时错误比特位的软值分布,提出了一种基于伴随向量和的软值翻转译码算法,该算法将伴随向量和中校验方程错误次数转化为错误比特位分布参数,在某个迭代次数时通过一种选择准则将部分比特位软值仅仅翻转一次,对于存在较多相关行的LDPC码,在几乎不增加译码复杂度(仅为O(N))的同时,较大程度上降低了误帧率.     

Alternative Schemes for Dynamic Secure VPN Deployment in UMTS

Three alternative schemes for secure Virtual Private Network (VPN) deployment over the Universal Mobile Telecommunication System (UMTS) are proposed and analyzed. The proposed schemes enable a mobile node to voluntarily establish an IPsec-based secure channel to a private network. The alternative schemes differ in the location where the IPsec functionality is placed within the UMTS network architecture (mobile node, access network, and UMTS network border), depending on the employed security model, and whether data in transit are ever in clear-text, or available to be tapped by outsiders. The provided levels of privacy in the deployed VPN schemes, as well as the employed authentication models are examined. An analysis in terms of cost, complexity, and performance overhead that each method imposes to the underlying network architecture, as well as to the mobile devices is presented. The level of system reliability and scalability in granting security services is presented. The VPN management, usability, and trusted relations, as well as their behavior when a mobile user moves are analyzed. The use of special applications that require access to encapsulated data traffic is explored. Finally, an overall comparison of the proposed schemes from the security and operation point of view summarizes their relative performance. Christos Xenakis received his B.Sc. degree in computer science in 1993 and his M.Sc. degree in telecommunication and computer networks in 1996, both from the Department of Informatics and Telecommunications, University of Athens, Greece. In 2004 he received his Ph.D. from the University of Athens (Department of Informatics and Telecommunications). From 1998–2000 was with the Greek telecoms system development firm Teletel S.A., where was involved in the design and development of advanced telecommunications subsystems for ISDN, ATM, GSM, and GPRS. Since 1996 he has been a member of the Communication Networks Laboratory of the University of Athens. He has participated in numerous projects realized in the context of EU Programs (ACTS, ESPRIT, IST). His research interests are in the field of mobile/wireless networks, security and distributed network management. He is the author of over 15 papers in the above areas. Lazaros Merakos received the Diploma in electrical and mechanical engineering from the National Technical University of Athens, Greece, in 1978, and the M.S. and Ph.D. degrees in electrical engineering from the State University of New York, Buffalo, in 1981 and 1984, respectively. From 1983 to 1986, he was on the faculty of Electrical Engineering and Computer Science at the University of Connecticut, Storrs. From 1986 to 1994 he was on the faculty of the Electrical and Computer Engineering Department at Northeastern University, Boston, MA. During the period 1993–1994 he served as Director of the Communications and Digital Processing Research Center at Northeastern University. During the summers of 1990 and 1991, he was a Visiting Scientist at the IBM T. J. Watson Research Center, Yorktown Heights, NY. In 1994, he joined the faculty of the University of Athens, Athens, Greece, where he is presently a Professor in the Department of Informatics and Telecommunications, and Director of the Communication Networks Laboratory (UoA-CNL) and the Networks Operations and Management Center. His research interests are in the design and performance analysis of broadband networks, and wireless/mobile communication systems and services. He has authored more than 150 papers in the above areas. Since 1995, he is leading the research activities of UoA-CNL in the area of mobile communications, in the framework of the Advanced Communication Technologies & Services (ACTS) and Information Society Technologies (IST) programmes funded by the European Union (projects RAINBOW, Magic WAND, WINE, MOBIVAS, POLOS, ANWIRE). He is chairman of the board of the Greek Universities Network, the Greek Schools Network, and member of the board of the Greek Research Network. In 1994, he received the Guanella Award for the Best Paper presented at the International Zurich Seminar on Mobile Communications.     

X-ray metrology for high-k atomic layer deposited HfxZr1−xO2 films

Hafnium-based dielectrics are the most promising material for SiO₂ replacement in future nodes of CMOS technology. While devices that utilize HfO₂ gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified Hf_xZr_1−xO₂ [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO₂ using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate.     

微电子封装的新进展领域及对SMT的新挑战

介绍了几种微电子新型封装材料,如LTCC、AIN、金刚石、AI-Sic和无铅焊接材料等,论述了正在发展中的新型先进封装技术,如WLP、3D和SIP等,并对封装新领域MEMS和MOEMS作了简介.最后,就这些新技术对SMT的新挑战作了些探讨.     

高速光纤综合通信网络平台研究

现代通信网络应能满足各种通信业务和通信容量日益发展的需求,实现话音、数据、视频、IP等业务的一体化综合交换和传输。在比较TDM、IP和ATM三种协议的基础上,提出"采用内置RPR和MPLS功能的MSTP平台"建设光纤综合通信网络平台的实现方法。MSTP采用SDH的数据帧结构,保持了SDH标准光接口、灵活分插低速信号、自愈环保护和功能强大的网管等优点,可对TDM、IP和ATM协议进行优化传输。     

A Fault-Tolerant Scheme for Mobility Management in PCS Networks

One of the most important and challenging issues in the design of personal communication service (PCS) systems is the management of location information. In this paper, we propose a new fault-tolerant location management scheme, which is based on the cellular quorum system. Due to quorum's salient set property, our scheme can tolerate the failures of one or more location server(s) without adding or changing the hardware of the systems in the two-tier networks. Meanwhile, with a region-based approach, our scheme stores/retrieves the MH location information in the location servers of a quorum set of the local region as much as possible to avoid long delays caused by the possible long-distance of VLR and HLR. Thus, it yields better connection establishment and update delay. Ming-Jeng Yang received the M.S. degree in computer science from the Syracuse University, New York, in 1991, and the Ph.D. degree in computer science from National Taiwan Normal University, Taiwan, in 2004. He is an associate professor in the Department of Information Technology, Takming College, Taiwan. His research interests include wireless networks, mobile computing, fault-tolerant computing, and distributed computing. He is a member of the IEEE Computer Society and the ACM. Yao-Ming Yeh received the B.S. degree in computer engineering from National Chiao-Tung University, Taiwan, in 1981, and the M.S. degree in computer science and information engineering from National Taiwan University, Taiwan, in 1983. In August 1991, he received the Ph.D. degree in the Department of Electrical and Computer Engineering, The Pennsylvania State University, Pa., U.S.A. He is a professor in the Department of Information and Computer Education, National Taiwan Normal University, Taiwan. His research interests include fault-tolerant computing, web and XML computing, and distributed computing.     

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail. This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4. Yu-Cherng Hung was born in Changhua, Taiwan, R.O.C., in 1964. He received the M. S. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1992, and the Ph.D. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2004. From Dec. 1986 to Jan. 2005, he was with the Division of Computer/Information, Chinese Petroleum Corp., Taiwan. He is currently an Assistant Professor with the Department of Electronic Engineering, National Chin-Yi Institute of Technology, Taiwan, R.O.C. His main research interests include analog circuit design, low-voltage VLSI design, and neural network applications. Dr. Hung is a Member of Phi Tau Phi Honorary Scholastic Society, IEEE, and the Institute of Electronics, Information, and Communications Engineers (IEICE). Bin-Da Liu received the Ph.D. degrees in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1983. Since 1977, he has been on the faculty of the National Cheng Kung University, where he is currently a Distinguished Professor in the Department of Electrical Engineering and the Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995, he has been a Consultant of the Chip Implementation Center, National Applied Research Laboratories, Hsinchu, Taiwan. He has published more than 200 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). His current research interests include low power circuit, neural network circuit, CMAC neural network, analog neural network architecture, design of programmable cellular neural networks, and very large-scale integration implementation of fuzzy/neural circuits and audio/video signal processors. Dr. Liu is a Fellow of IEEE and the Vice President of Region 10, IEEE Circuits and Systems Society. He served as a CAS Associate Editor of IEEE Circuits and Devices Magazine and an Associate Editor of IEEE Transactions on Circuits and Systems I: Regular Papers. He is serving as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Chung-Yang Tsai was born in Mian-Li, Taiwan, R.O.C. He received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001 and 2003, respectively. His research interests include very large-scale integration design and signal processing.     

Characterisation of electroplated Sn/Ag solder bumps

Environmental concerns as well as legal constraints have been pushing research on flip chip technology towards the development of lead-free solders and also to new deposition techniques [Z.S. Karim, R. Schetty, Lead-free bump interconnections for flip-chip applications, in: IEEE/CPMT 1nternational Electronics Manufacturing Technology Symposium, 2000, pp. 274-278, P. Wölflick, K. Feldmann, Lead-free low-cost flip chip process chain: layout, process, reliability, in: IEEE International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 27-34, M. McCormack, S. Jin, The design and properties of new, pb-free solder alloys, in: IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994, pp. 7-14, T. Laine-Ylijoki, H. Steen, A. Forsten, Development and validation of a lead-free alloy for solder paste applications. IEEE Transactions on Components, Packaging, and Manufacturing technology, 20(3) (1997) 194-198, D. Frear, J. Jang, J. Lin, C. Zhang, Pb-free solders for flip-chip interconnects, JOM, 53(6) (2001) 28-32].Binary and ternary tin alloys are promising candidates to substitute lead-content components. In this paper, we describe an electroplating technique for high density FlipChip packaging [M. Bigas, E. Cabruja, Electrodeposited Sn/Ag for flip chip connection, CDE (2003)]. An analysis using Auger Electron Spectroscopy (AES) together with additional Energy Dispersive Xray analysis (EDS) tests and Scanning Electron Microscope (SEM) analysis have been performed to optimize the reflow process of the electrodeposited bumps.     

Design of an ADC for subsampling video applications

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-of-merit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-μm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm². Jian Li received the Bachelor of Engineering (B.E.) degree in electronic engineering from Xi’an Jiaotong University, Xi’an, China, in 2003. He is currently working toward the Ph.D. degree at Microelectronics department, Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter design. Xiaoyang Zeng was born in Hunan Province, P.R. China on April 17, 1972. He received the B.S. degree from Xiangtan University, China in 1992, and the Ph.D. degree from Changchun Institute of Optics and Fine Mechanics, Chinese Academy of Sciences in 2001. From 2001 to 2003, he worked as a post-doctor researcher at the State-Key Lab of ASIC & System, Fudan University, P.R. China. Then he joined the faculty of Department of Micro-electronics at Fudan University as an associate professor. His research interests include information security chip design, VLSI signal processing, and communication systems. Prof. Zeng is the Chair of Design-Contest of ASP-DAC 2004 and 2005, also the TPC member of several international conferences such as ASCON 2005 and A-SSCC 2006, etc. Jianyun Zhang received the B.S., M.S. and Ph.D degree in electrical engineering from Fudan University, Shanghai, China in 1997, 2000 and 2006 respectively. From 2000 to 2002, he was with Alcatel microelectronics, Belgium, where he was involved in circuit design for GSM and GPRS. In 2002, he joined Trident microsystem, where he concentrated on the design of Video AFE including data converters and mixed signal circuits. In 2005, he joined Shihong microelectronics Corp., where he is now a director of mixed signal IC for video high speed interface. His research interests include data conversion, HDMI SerDes, and analog circuit design. Lei Xie received the Bachelor of Science (B.S.) degree in microelectronics from Nankai University, Tianjin, China, in 2005. He is currently working toward the M.S. degree at Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter. Huan Deng received the B.S. degree in microelectronics from Fudan University, Shanghai, P.R. China, in 2003. He is currently working toward the M.S. degree in microelectronics at the State Key Lab of ASIC & System, Fudan University. He is currently involved in the design of low-power, high-speed PLL’s. Yawei Guo received the B.S. and M.S. degree in electrical engineering from Fudan University in 1999 and 2002 respectively. From 2002 to August 2003, he was with Philips Semiconductors in Shanghai. Since August 2003, he has been with Shanghai MicroScience Integrated Circuits Co., Ltd., based in Shanghai, P. R. China. He has been leading a group and developing analog and mixed signal circuits. His research interests include high-speed data communication, data converters, and phase locked loops.     

On Fixed-Mobile Network Convergence

As the convergence in digital industry takes shape, the digital networks, both wireline and wireless, are also converging to offer seamless services and enhanced experience to the user. With the arrival of the mobile Internet the mobility is also moving into new areas, e.g., imaging, games, video, multimedia, and across different types of networks. In this paper we explore why, what, and how of the network convergence, and identify how the industry viewpoints align and differ. We also identify the key barriers to achieving true network convergence. We then discuss the role of the Internet Protocol (IP) as the common thread that enables network convergence, and the key industry and standards initiatives to actually provide solutions and the equipment to implement a cost-efficient and high performance converged network. Sudhir Dixit joined Nokia Research Center in 1996, where he is currently a Research Fellow and works on next generation wireless networks. From 1996 to 2003 he was a Senior Research Manager, focusing on IP/ATM, wireless, content networks, and optical networks. Prior to that he worked at NYNEX Science & Technology (now Verizon), GTE (now Verizon), Codex Motorola, Wang, Harris, and STL (now Nortel Europe Labs). He has published or presented over 150 papers, published three books, and holds 14 patents. He is on the Editorial Board of the IEEE Communications Magazine, Springer's Wireless Personal Communications Journal, and KIC's Journal of Communications and Networks. He received a B.E. degree from MANIT, Bhopal, India, an M.E. degree from BITS, Pilani, India, a Ph.D. degree from the University of Strathclyde, Glasgow, Scotland, and an M.B.A. degree from Florida Institute of Technology, Melbourne. He is a Fellow of IEE (UK) and IETE (India). He represents Nokia on the Steering Board of the Wireless World Research Forum, and is also Chair of the SIG on Self-Organization of Wireless World Systems.     

一个具有附益性及保序性算子的形态学非局部拓展

近年，形态学非局部拓展工作在图像处理领域受到众多关注.而附益性算子是经典形态学的最基本形式，也是形态学分析方法最重要的变换工具.为此，一些研究者就形态学非局部拓展中如何保持算子的附益性开展工作.本文从理论及实例两个方面说明，相关拓展工作为保持算子的附益性而丢失了保序性的不足；进一步，通过设计非局部权值的获取过程，并结合现有工作，本文提出了一个新的形态学非局部拓展，并定理证明了所得算子同时具备附益性及保序性两个重要性质；人工合成图像及自然图像上的仿真实验也表明了本文所提算法的有效性.