热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Hot hole gate current in surface channel PMOSFETs

This paper reports the observation of a new hot hole component of the gate current of p⁺-poly gate pMOS transistors. The phenomenon is characterized as a function of drain, gate, and substrate bias on devices featuring different oxide thickness and drain engineering options. The new hole gate current component is ascribed to injection into the oxide of substrate tertiary holes, generated by an impact ionization feedback mechanism similar to that responsible of CHannel Initiated Secondary ELectron injection (CHISEL) in nMOSFETs     

Impact ionization in InAlAs/InGaAs HFET's

The presence of an energy barrier to the transfer of holes from the channel to the gate electrode of InAlAs/InGaAs HFET's prevents the gate current from being a reliable indicator of impact ionization. Consequently, we have used a specially designed sidegate structure to demonstrate that due to the narrow bandgap of InGaAs, impact ionization takes place in the channel of these devices under normal operating conditions. The ionization coefficient was found to follow a classic exponential dependence on the inverse electric field at the drain end of the gate, for over three orders of magnitude     

Impact ionization and light emission in AlGaAs/GaAs HEMT's

Impact ionization and light emission phenomena have been studied in AlGaAs/GaAs HEMTs biased at high drain voltages by measuring the gate excess current due to holes generated by impact ionization and by analyzing the energy distribution of the light emitted from devices in the 1.1-3.1 eV energy range. The emitted spectra in this energy range can be divided into three energy regions: (i) around 1.4 eV light emission is dominated by band-to-band recombination between cold electrons and holes in GaAs; (ii) in the energy range from 1.5 to 2.6 eV energy distribution of the emitted photons is approximately Maxwellian; and (iii) beyond 2.6 eV the spectra are markedly distorted due to light absorption in the n⁺ GaAs cap layer. The integrated intensity of photons with energies larger than 1.7 eV is proportional to the product of the drain and gate currents. This suggests recombination of channel electrons with holes generated by impact ionization as the dominant emission mechanism of visible light     

Drastic reduction of gate leakage in InAlAs/InGaAs HEMT's using apseudomorphic InAlAs hole barrier layer

Impact ionization in the channel of InAlAs/InGaAs HEMT's was shown to be a reason for excess gate leakage current. Hot electrons in the high field region of the channel under the gate generate electron-hole pairs. The generated holes can reach the gate (gate leakage) as well as the source, the electrons flow to the drain (kink effect). The number of holes reaching the gate strongly depends on the valence band discontinuity. In order to increase this valence band discontinuity a thin pseudomorphic InAlAs layer with high Al-content was inserted in the spacer of an InAlAs/InGaAs HEMT. The efficiency of this hole barrier was measured by photocurrent and DC measurements, while its influence on transport characteristics was measured by Hall and RF measurements. A reduction of gate leakage by a factor of 200 is demonstrated     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

Two-dimensional analysis of the breakdown mechanism in theetched-groove silicon permeable base transistor

A two-dimensional, two-carrier simulation of a uniformly doped etched-groove permeable-base transistor which includes models for impact ionization and for Auger and Shockley-Read-Hall recombination is reported. It was found that for high current densities the breakdown voltage was reduced by channel avalanche. This mechanism was associated with a strong accumulation of electrons and holes in the source access region. In this region, the gate current remained low but the injection of electrons in the channel was enhanced, resulting in a degradation of the drain conductance and frequency performance     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2.5nm超薄栅短沟pMOSFETs在Vg=Vd/2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si-SiO2界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

Kink effect in an InAs inserted-channel InAlAs/InGaAs inverted HEMTat low temperature

The authors have investigated the kink effect In an InAs-inserted-channel InAlAs/InGaAs inverted HEMT at low temperature. The kink effect was not observed at both 77 and 300 K, but it appeared at 4.2 K. It is shown that the kink effect is caused at low drain voltages by the suppression of the drain current due to an increase in the source access resistance and at higher drain voltages by the increase in the drain current due to holes generated by impact ionization     

Field distribution in junction field-effect transistors at large drain voltages

An analytical approximation to the field distribution in the channel portion between gate and drain of the junction field-effect transistor is derived, assuming an infinitely small channel width-to-height ratio, and modified for finite channel widths by introducing an effective impurity concentration which depends on drain current. The approximation is applicable also in the limiting case of zero gate edge curvature, i.e., for Schottky-barrier gate. The theoretical field distribution is used to extract impact-ionization coefficients from published experimental data on gate current enhancement at large drain voltages. These impact-ionization coefficients agree with published data derived from bulk impact ionization.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2 .5 nm超薄栅短沟p MOSFETs在Vg=Vd/ 2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si- Si O2 界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

GaAs PHEMT器件的退化特性及可靠性表征方法

测量了应力前后Ga As PHEMT器件电特性的退化,指出了Ga As PHEMT阈值电压的退化由两个原因引起.栅极下Al Ga As层深能级的空穴积累可以解释阈值电压漂移中暂时性的、可恢复的那部分,积累在栅金属与半导体之间界面层的空穴可以解释阈值电压漂移中永久性的漂移.空穴积累来源于场助作用下电子的退陷和沟道中碰撞电离产生的空穴向栅极流动时被俘获.对高场下碰撞电离率的实验曲线进行拟合,得到碰撞电离率与器件沟道电场峰值的量化关系,可以对Ga As PHEMT器件的电性能和可靠性进行评估     

A better understanding of substrate enhanced gate current in VLSIMOSFETs and flash cells. II. Physical analysis

For pt. I see ibid., vol. 46, no. 2 (Feb. 1999). In this work-different physical mechanisms that could lead to the direct proportionality between I_G and I_B as the signature of substrate enhanced electron injection (SEEI), are analyzed in detail. By means of experiments and simulations we substantiate the current interpretation of SEEI in terms of an impact ionization feedback process and attribute a quantitatively negligible role to both drain avalanche hot electron injection and substrate electrons generated by the photons emitted by channel hot electrons. These experiments reconcile the current explanation of SEEI with the well known phenomenon of photon assisted minority carrier injection in the substrate, whose presence is clearly detectable in our devices, but whose impact on the gate current is estimated to be orders of magnitude smaller than that of impact ionization feedback     

High-breakdown-voltage AlInAs/GaInAs junction-modulated HEMT's(JHEMT's) with regrown ohmic contacts by MOCVD

A technology for increasing both the two-terminal gate-drain breakdown and subsequently the three-terminal-off-state breakdown of AlInAs/GaInAs high-electron-mobility transistors (HEMTs) to record values without substantial impact on other parameters is presented. The breakdown in these structures is dependent on the multiplication of electrons injected from the source (channel current) and the gate (gate leakage) into the channel. In addition, holes are generated by high fields at the drain and are injected back into the gate and source electrodes. These phenomena can be suppressed by increasing the gate barrier height and alleviating the fields at the drain. Both have been achieved by incorporating a p⁺-2DEG junction as the gate that modulates the 2DEG gas and by utilizing selective regrowth of the source and drain regions by MOCVD. The 1-μm-gate-length devices fabricated have two-terminal gate-drain and three-terminal-off-state breakdown voltages of 31 V and 28 V, respectively     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

Unusually abrupt switching in submicrometer thin-film transistorsusing a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 μm or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

New observation and the modeling of gate and drain currents inoff-state P-MOSFET's

The work reports new observations concerning the gate and drain currents measured at off-state conditions in buried-type p-channel LDD MOSFET devices. Detailed investigation of the observed phenomena reveals that 1) the drain current can be separated into two distinct components: band-to-band tunneling in the gate-to-drain overlap region and collection of holes generated via impact ionization by electrons inside the oxide; and 2) the gate current can be separated into two distinct components: the hot electron injection into the oxide and the Fowler-Nordheim electron tunneling through the oxide, At low negative drain voltage, the dominant component of the drain current is the hole generation inside the oxide. At high negative drain voltage, the drain current is essentially due to band-to-band tunneling, and it is correlated with the hot-electron injection-induced gate current     

Substrate current in short n-channel MOS transistors

Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law field-dependent correctly predicts the behaviour of the substrate current.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm