一种改进的焊盘模型参数提取技术

基于开路-短路去外嵌焊盘结构,提出了一种改进的焊盘模型参数提取方法。首先利用开路焊盘提取寄生电容,然后将剥离了寄生电容的短路焊盘等效电路划分为三个独立的网络进行进一步的分析,并提出了一种基于特征点的参数提取算法,同步提取寄生电阻和寄生电感参数。利用0.15μm GaN HEMT工艺对加工的开路短路焊盘测试数据进行了试验验证,并与传统的参数提取方法进行了比较。结果表明,本文提出的方法在测试频率范围0~50GHz内与测试结果吻合得更好。     

一种基于半分析法的HEMT小信号参数的提取方法

提出了一种基于半分析法的高速电子迁移率半导体晶体管小信号模型的提取方法.此方法是用测试结构的方法来提取焊盘电容和寄生电感,半分析法来提取寄生电阻,提高了寄生电阻的提取精度.在频率高达40 GHz的范围内,多偏置情况下模拟的S参数和测试的S参数曲线吻合良好,证明这种方法是正确的.     

一种“L-2L”传输线去嵌入方法的优化分析

介绍了一种基于硅基微波共面波导传输线的"L-2L"去嵌入技术的改进方法。该方法可更加精确地剥离在片器件S参数中探针焊盘寄生效应的影响。利用ADS软件对无焊盘的理想传输线结构进行了电磁仿真,确立了去嵌入结果精确度的判定标准。使用GSG微波探针提取了测试样品的S参数,推导了π型寄生参量等效电路模型中并联导纳Y不同位置(m=0,0.5,1)下左、右探针焊盘的ABCD矩阵,得到了去嵌入后在片器件的本征传输特性S参数,并结合电磁仿真对比。结果表明:m=1时,其S参数曲线与仿真结果最为接近(平均偏差量ΔS_(11)=18.431,ΔS_(21)=4.405,ΔS=11.418)。对于不同在片测试器件需要着重考虑m的取值。     

硅基片上射频集成无源器件的去嵌入表征方法研究

硅基片上射频集成无源器件进行S参数测试时不可避免受到焊盘寄生效应的影响。针对这一问题,提取了三组不同长度硅基共面波导型传输线的S参数,基于级联理论的三种去嵌入方法被用于传输线模型分布参数的精确表征,并结合电磁仿真综合对比。结果表明:相对于其他两种常用去嵌入方法,"混合"法得到的S参数曲线与无焊盘仿真最为接近(平均偏差S_(11)≤3.392%,S_(21)≤5.184%),且削弱了去嵌入过程中测量误差的影响,有效减少了分布参数曲线波动。     

RF CMOS工艺片上MOM电容的宽频带建模与验证

提出了一种新的基于RF CMOS技术的金属-氧化物-金属(MOM)电容宽频带建模方法。为了提高模型精度、扩展有效频带,模型在构造时加入了测试焊盘和输入/输出互连线的等效电路。测试结构是基于自身物理结构进行架构的,充分考虑了其在高频时引入的各种寄生效应。互连线模型考虑了高频时的趋肤效应。通过解析提取的方法,在低频时提取测试结构引入的容性和阻性寄生参数。采用物理公式计算互连线的等效电感和电阻以及高频下互连线产生的趋肤效应参数初值。对于模型拓扑结构和参数提取方法,采用40 nm RF CMOS工艺上设计所得连带测试结构MOM电容数据进行验证。在0.25～110 GHz的频率范围内,可得测试和仿真的S参数精确吻合。     

肖特基二极管毫米波等效电路模型参数提取方法

提出了一种肖特基二极管的毫米波等效电路模型参数提取方法。该方法利用开路测试结构确定焊盘电容,并结合短路测试结构确定馈线电感;基于直流I-V特性曲线和小信号S参数分别提取了寄生电阻并进行了对比分析;给出了本征元件随偏置电压的变化曲线。在频率高达40 GHz的范围内,截止和导通状态下S参数的模拟与测试数据吻合良好,验证了提取方法的有效性。     

薄膜体声波谐振器Mason模型参数的提取方法

为了正确分析和设计薄膜体声波谐振器(FBAR)器件,需要对谐振器Mason模型中的仿真参数(如机电耦合系数、介电常数及粘滞系数等)进行准确提取。通过简谐近似,在Mason模型中引入了厚度方向位移的横向分量,提高了参数提取的准确性。使用谐振器开路和短路图形的散射参数,提取了探针及测试焊盘的等效电路参数,对谐振器进行去嵌。根据拟合得到的模型参数,仿真了中心频率为5.43 GHz的滤波器。结果表明,采用该方法提取的模型参数仿真结果和滤波器探针测试曲线的通带形状吻合较好。     

印刷电路板焊盘参数的图像测量方法

提出了一种焊盘参数的图像测量方法.该方法首先利用圆形框获取包含被测焊盘区域,并对测量图像进行预处理;然后在圆形框上采用扫描法去除焊盘的泪滴区;其次在极坐标系下搜索焊盘边缘点,并利用最小二乘圆拟合法去除奇异边缘点、两次拟合法得到焊盘的边缘圆;最后经摄像机标定后计算出焊盘圆心和直径参数.方法中采用中值滤波、泪滴去除、奇异边缘点去除、系统线性标定等方法提高测量精度.测量结果表明,本测量方法精度高、速度快、稳定性好.已运用于自动光学测量仪中.     

0.35μm SOI CMOS器件建模技术研究

介绍了SOI技术的优势和器件建模的意义.针对0.35μmSOI CMOS工艺的开发,设计了用于建模的测试芯片.对于SOIMOSFET中存在的自加热等寄生效应设计了参数提取的流程,并设计了相应的测试方法.在得到所需的测试数据后,采用局部优化方法进行参数提取.最后通过模型仿真结果和测试数据的比较证明了建立的0.35μm SOI CMOS模型有较高的精度.     

一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

An approach to determine small-signal model parameters for InP-based heterojunction bipolar transistors

A new method for the extraction of the small-signal model parameters of InP-based heterojunction bipolar transistors (HBT) is proposed. The approach is based on the combination of the analytical and optimization technology. The initial values of the parasitic pad capacitances are extracted by using a set of closed-form expressions derived from cutoff mode S-parameters without any test structure, and the intrinsic elements determined by using the analytical method are described as functions of the parasitic elements. An advanced design system is then used to optimize only the parasitic parameters with very small dispersion of initial values. Good agreement is obtained between simulated and measured results for an InP HBT with 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points up to 40 GHz.     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

Impact of pad and gate parasitics on small-signal and noisemodeling of 0.35 μm gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters     

Direct measurement of Cbe and Cbc versusvoltage for small HBT's with microwave s-parameters for scaledGummel-Poon BJT models

A novel method for determining the junction capacitances versus voltage in heterojunction bipolar transistors (HBT's) using s-parameters at microwave frequencies is presented. This new technique has several advantages over traditional approaches, which include: (1) it profiles capacitance at greater forward bias; (2) it enables the direct measurement of minimum geometry transistors; (3) it allows for the accurate extraction of scaled HBT model parameters with emitter length; and (4) it results in improved pad parasitic deembedding for accurate modeling. Both the capacitance-voltage and large-signal HBT model results are shown     

电吸收调制器和DFB激光器集成器件的测量

提出了一种测量电吸收调制器和激光器集成器件芯片散射参数的新方法.根据电吸收调制器和封装寄生参数的等效电路模型,对测量的反射系数进行拟合,得到封装寄生参数和电吸收调制器的等效电路元件的参数值.通过分析发现测试封装寄生参数对电吸收调制器的测试结果有很大影响.去除了封装寄生参数的影响后,得到了调制器的反射和传输参数的真实频响特性     

An analytic method to determine GaAs FET parasitic inductances anddrain resistance under active bias conditions

An analytic technique to determine the parasitic inductances, source resistance, and drain resistance of the FET equivalent circuit is presented in this paper. The method exploits the frequency dependence of the extracted circuit parameters to determine the parasitic inductances and drain resistance from S-parameters measured over frequency for one active bias condition. Given a value for the parasitic gate resistance R _g, all of the other equivalent-circuit parameters are uniquely extracted. The method is fast and robust, making it suitable for in-line statistical process tracking, as well as device modeling. A process tracking example for a 12-wafer 1864-device sample and FET modeling results up to 40 GHz are also presented     

A new small-signal model for asymmetrical AlGaN/GaN HEMTs

A new small-signal model for anisomerous AIGaN/GaN high electron mobility transistors (HEMTs) is pro-posed for accurate prediction of HEMT behavior up to 20 GHz. The parasitic elements are extracted from both cold-FET and pinch-off bias to obtain more precise results and the intrinsic part is directly extracted. All the parameters needed in this process are determined by the device structure rather than optimization methods. This guarantees consistency between the parameter values and the component's physical meaning.     

A peeling algorithm for extraction of the HBT small-signal equivalent circuit

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base. The expressions for the base-collector capacitances are valid for both the hybrid-/spl pi/ and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy.     

Analytical model and parameter extraction to account for the pad parasitics in RF-CMOS

A model which considers the pad parasitic effects when performing on-wafer S-parameter measurements on microwave devices fabricated on silicon substrates is presented. The model parameters are directly determined using a simple and analytical measurement-based method, allowing the electrical representation of the complete test structure using an equivalent circuit. The validity of the model is verified by achieving excellent agreement between simulated and experimental data up to 55GHz. In addition, a recently reported simplified deembedding procedure is improved and compared to a conventional one to study its validity as frequency increases.