Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

A new high-density low-voltage SSIMOS EEPROM cell

An efficient low-voltage EEPROM cell is described which occupies an area of 135 µm²when fabricated with 3-µm CMOS technology. To charge and discharge the floating gate, the device relies on Fowler-Nordheim tunneling of electrons between the floating gate and a narrow window of the device channel region. In addition, the control gate is positioned so as to shield the remaining portion of the floating gate from the substrate. The cell can be programmed in 10 ms with a nominal WRITE voltage of 16 V and an ERASE voltage of 12 V. The WRITE/ERASE endurance of the cell is in excess of 10⁶cycles, and the data retention has been shown to be greater than 10 years at 125°C.     

A 128-pixel CMOS image sensor with integrated analog nonvolatilememory

A 128-pixel complementary metal-oxide-semiconductor (CMOS) image sensor array with analog nonvolatile storage for each pixel has been realized in a 1.5-μm single-poly standard CMOS/EEPROM technology and successfully tested. The integrated nonvolatile memory allows an offset correction for each sensor element, cancellation of the fixed pattern noise, and compensation of the background illumination. The sensor array can also learn a presented pattern and store it in its analog nonvolatile memory just by “seeing”. The stored pattern can be read out directly or, in combination with the optical input, it can be used for pattern recognition or motion detection. The required programming circuitry for the analog memory has been integrated on the same chip     

A 35-ns 64K EEPROM

An extremely high-speed 8K/spl times/8 EEPROM has been fabricated in a 2-/spl mu/m double-poly CMOS floating gate technology. A typical address and chip enable access time of 35 ns has been achieved. Through a metal option, the device is compatible with 28-pin EEPROM, SRAM, or EPROM, or is a 24 pin bipolar PROM substitute. The high-speed access has been achieved with a fast single-ended sense amplifier, high-speed static bootstrapping techniques, a novel combination of static CMOS and depletion load technology, substrate bias, and high-performance layout. A new column and byte latch circuit implements a page-mode programming feature. Column redundancy implemented with EEPROM fuses increases manufacturability.     

一种应用于可编程模拟电路的EEPROM单元

为改善传统EEPROM在可编程模拟电路应用中的不足,提出了一种新型的单层多晶EEPROM单元结构,与常见的单层多晶EEPROM结构相比,该结构采用双N阱、附加栅结构实现,与标准数字CMOS工艺兼容,具有写入电流控制准确、阈值电压低的特点.通过对器件的分析及仿真,验证了该结构在模拟电路应用中的有效性.     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

A 60-ns 16-Mb flash EEPROM with program and erase sequencecontroller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm×2.0 μm and a chip size of 6.5 mm×18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process     

Electrical characterization and reliability of double-doped drain MOS transistors compatible with an EEPROM process

Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manufactured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at V_ds = 10 V, V_gs = 5 V. The observed degradation seems to be mainly due to acceptor-type interface state creation near the drain junction.     

A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

A 1.5 V single-supply one-transistor CMOS EEPROM

Describes a 1.5 V single-supply one-transistor p-channel CMOS EEPROM array which is fabricated with a double polysilicon gate 7-mask CMOS technology. Avalanche injection and Fowler-Nordheim emission are used as very low power programming mechanisms. A thin oxide of 28 nm allows write and erase voltages below -30 V. They are generated on-chip by voltage multipliers and fed by 1.5 V logic circuitry to the matrix array. Results measured on a 16/spl times/4 bit word-erasable test array are presented.     

高兼容CMOS工艺嵌入EEPROM技术

电可擦除只读存储器是非易失性存储器。文章介绍了高兼容常规CMOS工艺的一种嵌入式电可擦除只读存储器设计与工艺技术,对电可擦除只读存储器单元、高压MOS器件的结构与技术进行了研究。研究结果表明,我们设计的0．8μm电可擦除只读存储器单元Vpp电压在13V～15V之间能够正常工作,擦写时间小于500μs,读出电流大于160μA／μm;在普通CMOS工艺基础上增加了BN＋埋层、隧道窗口工艺,成功应用于含嵌入电可擦除只读存储器的可编程电路的设计与制造。     

标准CMOS工艺栅控Si-LED设计与制备

采用新加坡半导体制备有限公司的0.35um EEPROM双栅标准CMOS工艺设计和制备了U型Si-LED发光器件。器件结构采用P+-N+-P+-P+-P+-N+-P+-P+-P+-N+-P+叉指结构形成U型器件,外部的两个P+区为保护环,在相邻的内部两个P+区之间使用多晶硅作为栅极来调控LED的正偏发光。使用奥林巴斯IC显示镜测得了硅LED实际器件的显微图形,并对器件进行了电学的正反向I-V特性测量。器件在室温下正向偏置,在100～140mA电流下对器件进行了光功率的检测,发光峰值在1089nm处。结果表明,器件发光功率随着栅控电压偏置电流的增加而增加。     

An excellent weight-updating-linearity EEPROM synapse memory cellfor self-learning Neuron-MOS neural networks

A new synapse memory cell employing floating-gate EEPROM technology has been developed which is characterized by an excellent weight-updating linearity under the constant-pulse programming. Such a feature has been realized for the first time by employing a simple self-feedback regime in each cell circuitry. The potential of the floating gate is set to the tunneling electrode by the source follower action of the built-in cell circuitry, thus assuring a constant electric field strength in the tunnel oxide at each programming cycle independent of the stored charge in the floating gate. The synapse cell is composed of only seven transistors and inherits all the advanced features of the original six-transistor cell, such as the standby-power free and dual polarity characteristics. In addition, by optimizing the intra-cell coupling capacitance ratios, the acceleration effect in updating the weight has also been accomplished. All these features make the new synapse cell fully compatible with the hardware learning architecture of the Neuron-MOS neural network. The new synapse cell concept has been verified by experiments using test circuits fabricated by a double-polysilicon CMOS process     

An EEPROM for microprocessors and custom logic

An EEPROM extension to a 2.5-/spl mu/ n-well CMOS technology has been developed. In this technology an EEPROM has been designed that is suitable for integration with (existing) microprocessors in a baseline 5 V technology. A 2K EEPROM memory module, usable as a building block in a cell library for custom logic, measures 3.2 mm/SUP 2/ with a memory cell area of 440 /spl mu/m/SUP 2/.     

A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-$muhbox m$standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2$muhbox m^2$three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external$hboxI^2hboxC$master device such as universal$hboxI^2hboxC$serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9$hbox mm^2$. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications.     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

Improved EEPROM tunnel- and gate-oxide quality by integration of alow-temperature pre-tunnel-oxide RCA SC-1 clean

The effects of integration of a low-temperature RCA standard clean-1 (SC1) on the tunnel- and gate-oxide charge-to-breakdown (Q_BD) and voltage ramped dielectric breakdown (VRDB) distribution in a 0.7 μm CMOS EEPROM process technology were studied. A low-temperature (<65°C) SC1 used to clean the wafer surface prior to tunnel oxidation resulted in a significantly higher tunnel-oxide Q_BD, as well as improved gate-oxide Q_BD and mode-B failure rates compared to that for a traditional high temperature (>80°C) SC1. The reduced silicon diode etchrate of the low-temperature SC1 allowed for additional gate-oxide annealing during the gate oxidation cycle, while keeping the overall thermal budget (Dt)^1/2 for the technology equivalent to that with the higher temperature SC1. This resulted in improved gate-oxide VRDB distributions and QED values on large capacitor structures. The tunnel-oxide QBD improvement was most likely due to reduced surface roughness in the tunnel-oxide window regions with the lower temperature SC1. The process including the low-temperature SC1 was also proven to provide equivalent yield to the process with the high temperature SC1 on a 0.7 μm, 7 nS 128 macrocell EEPROM programmable logic device     

A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO₂ tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.