A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digitalconversion of a 10 MHz FM signal

In many wireless applications, it is necessary to demodulate and digitize frequency or phase modulated signals. Most commonly, this is done using separate frequency discrimination and analog-to-digital (A/D) conversion. In low-cost IC technologies, such as CMOS, precise analog frequented discrimination is not practical, so the A/D conversion is usually performed in quadrature or at a nonzero intermediate frequency (IF) with digital frequency discrimination. While practical, the approach tends to require complicated A/D converters, and accuracy is usually limited by the duality of the A/D conversion. This paper presents an alternative structure, referred to as a delta-sigma frequency-to-digital converter (ΔΣFDC), that simultaneously performs frequency demodulation and digitization. The ΔΣFDC is shown to offer high-precision performance with very low analog complexity. A prototype of the key component of the ΔΣFDC has been fabricated in a 0.6 μm, single-poly, CMOS process. The prototype achieved 50 kSample/s frequency-to-digital conversion of a 10 MHz frequency-modulated signal with a worst case signal-to-noise-and-distortion ratio of 85 dB and a worst case spurious-free dynamic range of 88 dH     

Multibit oversampled ΣΔ A/D converters as front end forCD players

A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta (ΣΔ) A/D converter in combination with digital signal processing. The use of ΣΔ type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

The design of sigma-delta modulation analog-to-digital converters

The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta (ΣΔ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Σ2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-μm CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm², and has achieved a measured dynamic range of 89 dB     

Digital detection of instability of higher order bandpasssigma-delta converters

A digital method of stabilising higher order sigma-delta converters is presented. Results are given for a third order bandpass ΣΔ converter with three continuous time LC filters tuned to 1/4 of clock frequency f_c     

CMOS oversampling ΔΣ magnetic-to-digital converters

In this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

Granular quantization noise in a class of delta-sigma modulators

The trend toward digital signal processing in communication systems has resulted in a large demand for fast accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made ΔΣ modulator-based A/D converters attractive solutions. However, rigorous theoretical analyses have only been performed for the simplest ΔΣ modulator architectures. Existing analyses of more complicated ΔΣ modulators usually rely on approximations and computer simulations. In the paper, a rigorous analysis of the granular quantization noise in a general class of ΔΣ modulators is developed. Under the assumption that some input-referred circuit noise or dither is present, the second-order asymptotic statistics of the granular quantization noise sequences are determined and ergodic properties are derived     

CMOS fully-differential bandpass ΣΔ modulator usingswitched-current circuits

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z¹→-z²) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²     

A multibit delta-sigma audio DAC with 120-dB dynamic range

A 24-bit 192-kHz sample-rate digital-to-analog converter (DAC) achieves 120-dB A-weighted dynamic range in the 20-kHz band, and consumes 310 mW with a 5-V power supply. A third-order five-bit ΔΣ architecture optimized for high-end consumer audio has been developed and used. A switched-capacitor (SC) DAC combined with infinite-impulse response (IIR) and finite-impulse response (FIR) filters is employed to increase immunity to clock jitter, and reduce analog power. Partial-range dynamic element matching (DEM) enhances mismatch shaping with reduced circuit overhead. The 7.8-mm² chip fabricated in 0.5-μ m CMOS integrates a stereo DAC and all functions required for DVD-audio playback     

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process     

The implementation of digital echo cancellation in codecs

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5-μm technology using ΣΔ modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary     

Architecture, design, and test of continuous-time tunableintermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP ΔΣ) modulators. Bandpass modulators sampling at high IFs (~100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP ΔΣ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f_T) of 80 GHz and a maximum frequency of oscillation (f_MAX) of about 130 GHz. Operating from ±5-V power supplies, a fabricated 180-MHz IF fourth-order ΔΣ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (~1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (~60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements     

A 3.2-GHz second-order delta-sigma modulator implemented in InP HBTtechnology

This paper presents a second-order delta-sigma (ΔΣ) modulator fabricated in a 70 GHz (f_T), 90 GHz (f_max) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from ±5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first ΔΣ modulator in III-V technology with ideal performance and provides the foundation for extending the use of ΔΣ modulator analog-to-digital converters (ADC's) to radio frequencies (RF)     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by localfeedback loops

The design of a low-power, low-voltage, 12-b 8-kHz bandwidth ΣΔ modulator for high-quality voice that consumes only 0.34 mW at 1.95 V supply is described. The modulator employs a special architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multistage ΣΔ modulators, this architecture is very tolerant to the modest dc gain of low voltage op-amps. The architecture, together with special circuit techniques, permits a low-voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2-μm CMOS technology