Impact of polysilicon dry etching on 0.5 μm NMOS transistorperformance: the presence of both plasma bombardment damage and plasmacharging damage

Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 μm NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Analysis of gate oxide thickness hot carrier effects in surfacechannel P-MOSFET's

The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in ΔV_t for thinner oxides are found to play secondary roles     

Characterization and optimization of metal etch processes tominimize charging damage to submicron transistor gate oxide

Two metal etch systems are compared in terms of their impacts on submicron transistor gate oxide integrity. The magnetically enhanced RIE (MERIE) system is shown to cause significant gate oxide damage with a pronounced radial dependence. This damage does not occur on wafers etched in the hexode-type RIE system. Experimental work on the MERIE system shows that the presence of the magnetic field during the aluminum overetch and barrier metal etch portion of the process is the primary cause for the observed gate oxide damage. This damage can be minimized by reducing or eliminating the magnetic field during the overetch step     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

Atomic Layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics for future high-speed DRAM with enhanced reliability

Atomic layer-deposited (ALD) Si-nitride/SiO/sub 2/ stack gate dielectrics were applied to high-performance transistors for future scaled DRAMs. The stack gate dielectrics of the peripheral pMOS transistors excellently suppress boron penetration. ALD stack gate dielectrics exhibit only slightly worse negative-bias temperature instability (NBTI) characteristics than pure gate oxide. Enhanced reliability in NBTI was achieved compared with that of plasma-nitrided gate SiO/sub 2/. Memory-cell (MC) nMOS transistors with ALD stack gate dielectrics show slightly smaller junction leakage than those with plasma-nitrided gate SiO/sub 2/ in a high-drain-voltage region, and have identical junction leakage characteristics to transistors with pure gate oxide. MCs having transistors with ALD stack gate dielectrics and those with pure gate oxide have the identical retention-time distribution. Taking the identical hole mobility for the transistors with ALD stack gate dielectrics to that for the transistors with pure gate oxide both before and after hot carrier injection (previously reported) into account, the ALD stack dielectrics are a promising candidate for the gate dielectrics of future high-speed, reliable DRAMs.     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Effect of plasma poly etch on effective channel length and hotcarrier reliability in submicron transistors

The effective channel length (L_eff)) variation resulting from exposure to the plasma during the poly-etch step was investigated. The plasma induced charging effect was also studied using gate polysilicon antenna structures. It was found that, due to the poly etching, the L_eff variation has a larger impact on the fully processed transistor transconductance characteristics than the charging effect in the gate oxide region. It is believed that the damage in the LDD region, which gives rise to the L_eff variation, imposes a serious hot carrier reliability problem     

Electrical and Reliability Characteristics of 12- Å Oxynitride Gate Dielectrics by Different Processing Treatments

Various ultrathin oxynitride gate dielectrics of similar thickness (~1.2 nm) fabricated by a combination of an in situ steam generated and remote plasma nitridation treatment (RPN), an RPN with rapid thermal NO annealing (RPN-NO), and an RPN with rapid thermal O₂ annealing (RPN-O₂) are reported in this paper. The RPN-NO gate dielectric films show superior interface properties including relatively high nitrogen concentration near the poly-Si/oxide interface and smooth interfaces, excellent electrical characteristics in terms of lower leakage current, better electron and hole channel mobility, higher drive current, and significantly improved reliability such as stress-induced leakage current, hot carrier injection, and negative bias temperature instability, compared to other gate dielectrics fabricated by different processes.     

Application of anodization in Oxygen plasma to fabrication of GaAs IGFET's

Anodic oxide grown in oxygen plasma has been used to fabricate the gate insulator of GaAs insulated-gate field-effect transistors (IGFET's), by patterning the gate electrode of 1.2 µm in length with the dry etching process. It is found that the oxidation process does not damage the electrical property of the channel layer. However, the trap states at the interface between the oxide and the channel affect the low-frequency characteristics, especially at positive gate voltage. The IGFET's show a good high-frequency performance comparable to GaAs MESFET's. The following characteristics are confirmed from the measurement of the S-parameters and the equivalent circuit analysis; the maximum stable power gain is 11.4 dB at 8 GHz, the cut-off frequency of the unilateral power gain is 48 GHz, and the intrinsic gain-bandwidth product is 18 GHz. The minimum noise figure is measured to be 4.8 dB at 8 GHz.     

Local iterative Monte Carlo analysis of electron-electroninteraction in short-channel Si-MOSFETs

The effects of electron-electron interaction on the electron distribution, substrate current, and gate current in short n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied using the local iterative Monte Carlo (LIMC) approach. The complete distribution function is always available at each step of this approach and with reduced noise with respect to standard Monte Carlo (MC) simulation. Therefore, electron-electron interaction can be evaluated efficiently using scattering rates, allowing one to examine hot carrier effects that may play an important role for device reliability and characterization. Results for MOSFETs with channel length as short as 25 nm show that electron-electron interaction leads to an increase of the high energy tail of the electron distributions at the transition from channel to drain. The electron density around 3 eV is significantly increased even if the applied voltage is in the 1.0 V range     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Charge injection using gate-induced-drain-leakage current forcharacterization of plasma edge damage in CMOS devices

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's     

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

The study reported herein examines and compares damage to n-channel and p-channel metal-oxide-silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μm channel length and with a 90 Å thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.     

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.     

Modeling of 10-nm-scale ballistic MOSFET's

We have performed numerical modeling of nanoscale dual-gate ballistic n-MOSFET's with ultrathin undoped channel, taking into account the effects of quantum tunneling along the channel and through the gate oxide. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the sub-10-nm devices potentially suitable for logic and memory applications, though their parameters are rather sensitive to size variations     

Reliability issues of scaled-down MOS transistors for gigabit circuits

The basic reliability issues of very small MOS transistors are addressed in this review and reliability constraints, such as trap-assisted tunneling, current increase at corner regions, oxide stability, oxide damage during processing, and hot carrier degradation are discussed. No major problems are expected for MOS transistors scaled down to their physical limits.     

Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed