Tunable operational transconductance amplifier with extremely high linearity over very large input range

A simply fully-differential transconductor is presented that achieves, based on cancellation of first and higher order nonlinearities, +or-0.7% linearity error over a +or-6.4 V differential input range for +or-5 V power supplies. Common-mode input signals are cancelled at the output. The transconductance can be tuned at least by a factor 3 and f/sub (-3dB)/ is 63 MHz for 10 mu m channel length.<>     

CMOS four-quadrant multiplier using bias offset crosscoupled pairs

A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.<>     

High frequency wide range CMOS analogue multiplier

A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2 mu m process parameters are given. The circuit has an input range of +or-4 V and linearity error less than 1% for inputs up to +or-3 V. The magnitude and phase response are very flat; even at 30 MHz the change in the magnitude is less than 0.086 dB (1%) and the phase shift is less than 5 degrees .<>     

A linear CMOS transconductance element of an adaptively biased source-coupled differential pair using a quadritail cell

A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistor-arrays and discrete components on a breadboard.     

Highly linear four quadrant analogue BiCMOS multiplier for +or-1.5 V supply operation

A highly linear four-quadrant analogue BiCMOS multiplier is presented. It operates with +or-1.5 V supplies and with 2 V peak to peak input and output signal wings. It is based on the use of crosscoupled, voltage biased differential pairs. Experimental results of a CMOS test chip are presented that confirm the proposed structure.<>     

New CMOS linear transconductor

A new transconductor is proposed which uses a bias feedback technique and has a simple configuration and a good high-frequency performance. The proposed transconductor is tunable by adjusting the bias current, and suitable for application to highly linear continuous-time filters. Experimental results show that the total harmonic distortion (THD) of the output current is less than 1% for the differential/single-ended input signals of up to 6.0 V/4.3 V (peak-to-peak) when the supply voltages are +or-5 V.<>     

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.     

Open loop fibre optic gyroscope with phase shift nulling signal processing

A simple analogue phase tracking circuit for the fibre gyroscope is described. The system provides a linear output from an open loop gyroscope configuration over a range in Sagnac phase shift >+or-500 degrees Sagnac, with good linearity and relatively low noise and drift. The use of this demodulator in low-cost medium grade fibre gyroscope applications is projected.<>     

A Novel CMOS OTA Based on Body-Driven MOSFETs and its Applications in OTA-C Filters

The operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Traditional OTAs suffer linearity reduction as a result of the MOSFET scaling trend. In this paper, a body-driven (BD) CMOS triode-based fully balanced OTA is proposed to achieve low distortion and linear frequency tuning. In contrast to the gate-driven based OTAs (that have the tradeoff of input and tuning range), BD-based OTAs operate under a wide input range over a large tuning interval. Common-mode (CM) feedforward and CM feedback schemes have been developed so that the CM voltage varies only 7 mV over a tuning range of 1.2 V = Vtune = 1.58 V. Using the 0.18-mum N-well CMOS process, a third-order elliptic low-pass filter is implemented with the aid of the proposed OTA. The total harmonic distortion ( is -45 dB for 0.8-V peak-peak (Vpp) fully differential input signals. A dynamic range of 45 dB is obtained with the OTA's noise integrated over 1 MHz.     

Novel Voltage-Tunable, Low-Voltage Linear CMOS Transconductor

A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-m n-well process parameters and a power supply of ±2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ±1.2 V. The THD for a differential input voltage of 1V _pp at 1 kHz is 1.3%.     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

CMOS four-quadrant multiplier using bias feedback techniques

A new wide-range CMOS four-quadrant multiplier using the bias feedback techniques is presented. Simulation results show that for a power supply of ±5 V, the linear range is over 14 V and the linearity error is less than 1% over a 13 V input range. Experimental results show that the linear range is over ±1 V. The results will be useful in analog signal processing applications     

Design and application of precise analog computational circuits

New versatile building blocks for implementing analog functional circuits such as a multiplier, a squarer, and a square rooter based on functional terms of a differential input circuit are proposed and implemented in 0.25 um CMOS process. The input range of these circuits is over  ±1.0 V with a high linearity of less than 4% for 3.3 V power supply. The  ?3 dB bandwidth of all discussed circuits has been measured to over 200 MHz. The functional circuit size is 340 μm², and its typical power consumption is about 90 uW.     

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

Reliability of code density test for high resolution ADCs

The effect of convertor internal noise on its output code histogram is analysed. Simulations show that large linearity errors, including missing codes, may vanish when sufficient noise is experienced. Consequently, the code density test is likely to yield a differential nonlinearity error within +or-0.5 LSB for any high accuracy noisy convertor.<>     

Transconductance enhancement in bulk-driven input stages and its applications

Two different circuit techniques to enhance the effective transconductance of a CMOS bulk-driven differential input stage are presented in this paper. Both approaches rely on a partial positive feedback, which leads to improved values for the DC gain and the gain-bandwidth product. The operation principle of the first solution is based on modifying the effective conductance of the active load of the input stage, while the second method acts directly on the input differential pair. The suitability of the presented techniques is demonstrated by the design of operational transconductance amplifiers operating at two different supply voltages, i.e., 2.4 and 1.0 V. Besides, the overall design of two applications, namely a 3 V input/output rail-to-rail operational amplifier with high linearity and a 1.2 V second-order OTA-C low-pass filter, is addressed. Simulated results obtained in standard 0.35 μm CMOS technology demonstrate the applicability of the solutions introduced.     

A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers

The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs. Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-/spl mu/m CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower. Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV//spl radic/Hz input referred noise voltage density while drawing 4 mA from 1.8 V.     

Adaptively biased linear transconductor

This paper describes a new circuit topology of a linear transconductor. The conventional differential pair (CDP), with a constant tail current, is linearized by an adaptive biasing scheme , and the only extra elements added to the differential pair are source followers. Compared to the CDP, the proposed circuit achieves similar speed and noise performance, but the common-mode rejection is compromised at the expense of tremendous improvement in linearity. While operating from a 1.8-V power supply in a 0.18-/spl mu/m CMOS process, the simulated variation in g/sub m/ for 1-V/sub p-p/ and 2-V/sub p-p/ differential input is 1.2% and 22%, respectively. Also, the THD performance for a 1-V/sub p-p/, 1-MHz differential sinusoidal input is -65 dB, which is about a 40-dB improvement over the CDP.     

二极管型非制冷红外探测器的前端电路设计

设计了一种二极管型非制冷红外探测器的前端电路,该电路采用Gm-C-OP积分放大器的结构,将探测器输出的微弱电压信号经跨导放大器(OTA)转化为电流信号,再经电容反馈跨阻放大器(CTIA)积分转化为电压信号输出。该OTA采用电流反馈型结构,可以获得比传统OTA更高的线性度和跨导值。输入采用差分结构,可以有效地消除环境温度及制造工艺对探测器输出信号的影响。电路采用0.35 m CMOS工艺进行设计并流片,5 V电源电压供电。Gm-C-OP积分放大器总面积0.012 6 mm2,当输入差分电压为0~5 mV时,测试结果表明:OTA跨导值与仿真结果保持一致,Gm-C-OP积分放大器可实现对动态输入差分信号到输出电压的线性转化,线性度达97%,输出范围大于2 V。     

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.