基于LTCC超材料基板的小型化V波段毫米波微带天线设计

本文介绍了一种基于LTCC超材料（metamaterials）基板的小型化V波段毫米波微带天线设计。通过HFSS仿真软件获得LTCC超材料基板的S参数,使用改进的S参数提取方法获得材料的等效介电常数和磁导率。利用LTCC超材料替代普通介质基板,实现了毫米波微带天线的小型化,并与常规介质基板天线的性能进行了对比。     

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.     

真空镀膜中基底预应力的有限元分析

真空镀膜过程中,基底因支撑、温度梯度造成的应变会对最终的薄膜-基底系统的面形产生影响。用有限元方法对不同支撑方式下不同尺寸基底的预应力以及烘烤过程中基底内部温度梯度造成的热应力进行了分析和计算,得到基底表面变形的峰谷值,并给出了不同工况下基底形变的等值线图。对于尺寸超过200 mm的基底,自重变形量和热应力变形量比较大,是影响最终薄膜面形的重要因素;装夹时随着基底倾角的增大,基底的形变与应力呈减小趋势;同样结构尺寸情况下,熔融石英基底的自重变形量略大于BK7基底,热变形量远小于BK7基底;热应力对基底预应力的贡献较大。     

一维热应力模型在调Q短脉冲激光除漆中的应用

讨论了热应力在短脉冲激光清洗油漆过程中的作用,从一维热传导方程出发,计算了由热膨胀产生的热应力以及根据粘附力公式计算出了油漆的粘附力.通过比较热应力与粘附力大小,得到激光清洗油漆的条件,进而建立一维短脉冲激光除漆模型.根据此模型可计算出:波长为1064 nm,脉宽为10 ns的激光清除铁基底上厚度为40μm橙色漆的清洗阈值为0.5 J/cm2;不同能量密度下使得油漆脱落所需的激光作用时间;激光脉冲作用过程中铁基底的温度变化情况.实验所测得的清洗阈值为0.57 J/cm2,与理论结果接近.实验与理论都表明当能量密度过高时,铁基底的温度升高很大,超过其熔点,铁基底被损坏.并考虑了激光清洗铝基底上油漆的情况.     

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.     

晶片键合在AlGaInP发光二极管中的应用

(AlxGa1-x)0.5In0.5P高亮度发光二极管是在GaAs衬底上匹配外延的，它的外量子效率受限于吸收光线的GaAs衬底。LED晶片键合技术可以把LED外延片和GaP透明衬底、金属镜面衬底或蓝宝石衬底结合以提高出光效率。本文对上述三种晶片键合的器件制备过程和器件特点进行了描述。     

激光淬火基体对镀铬层界面剪切强度的影响

为了揭示激光淬火预处理基体提高镀铬身管寿命的机理,采用多裂纹拉伸技术分别对激光淬火处理和激光未处理基体上的镀铬层界面剪切强度进行了测量,发现激光淬火基体可以提高镀铬层界面剪切强度77.7%,并从基体与铬层的界面材料结构和力学两个方面进行了分析。结果表明,激光预处理的界面是连续过渡的,而原始基体的界面存在一个过渡;激光淬火基体表面残余压应力的存在提高了铬层的断裂应力;基体表面硬度的提高减小了最大裂纹间距。     

Numerical simulation of GaAs MESFETs with a p-buffer layer on asemi-insulating substrate compensated by deep traps

A numerical analysis of GaAs MESFETs with a p-buffer layer on a semi-insulating substrate is performed in which impurity compensation by traps in the substrate is considered. It is shown that the use of a thick p-buffer layer results in a lower device current due to the formation of a steep barrier at the channel-substrate interface. It is also shown that with higher trap and acceptor densities in the substrate, the drain current is reduced due to the decrease in the substrate current. This decrease occurs because a negative-space-charge layer is formed in the substrate. It is demonstrated that when the p-buffer layer is fully depleted, its acceptors play the same electrical role as the acceptors within the space-charge region of the semi-insulating substrate. Thus, using a thick p-buffer layer has the same effect as using a substrate with a high density of traps, i.e. it minimizes the short-channel effects in GaAs MESFETs. Therefore, if the trap density in the substrate is low, the short-channel effects can be reduced by introducing a p-buffer layer or a buried p-layer     

激光预处理基体细化铬层晶粒的电镀机理研究

为了揭示激光淬火预处理钢基体细化镀铬层界面晶粒的电镀机理,采用理论和试验相结合的方法进行了理论分析和试验验证。用化学腐蚀法制备了铬层/激光离散预处理基体界面的两侧（铬层界面与基体界面）,利用扫描电镜研究了铬层界面晶粒形貌,利用激光粗糙度仪测量了基体界面粗糙度;借助电镀理论构建了以过电位为中间变量的铬层界面晶粒尺寸和基体界面粗糙度关系分析模型;取得了粗糙度与晶粒尺寸呈正比的试验结果和粗糙度与晶粒尺寸呈正比的理论关系,得到了淬火预处理钢基体细化镀铬层界面晶粒的电镀机理。结果表明,激光淬火预处理钢基体得到的较小粗糙度可以提高过电位,过电位的提高减小了铬层界面晶粒尺寸。这一结果对进一步解释激光淬火预处理可以提高基体/铬层界面结合强度是有帮助的。     

碲锌镉衬底的化学机械抛光液研究

作为碲锌镉衬底表面加工的重要工序,化学机械抛光(Chemical Mechanical Polishing, CMP)的加工效果决定了碲锌镉衬底的表面质量和生产效率。抛光液是CMP的关键影响因素之一,直接影响衬底抛光后的表面质量。对碲锌镉衬底CMP工艺使用的抛光液进行了研究,探究了以二氧化硅溶胶和过氧化氢为主体的抛光液体系在不同pH值、不同磨料浓度下对衬底抛光表面质量和去除速率的影响。结果表明,使用改进后的抛光液体系对碲锌镉衬底进行CMP,能够在获得超光滑表面的同时实现高效率加工,为批量化制备高表面质量的碲锌镉衬底奠定了良好基础。     

Improvement of the Crystallinity of Silicon Films Deposited by Hot-Wire Chemical Vapor Deposition with Negative Substrate Bias

We have investigated the effect of negative substrate bias on microcrystalline silicon films deposited on glass and stainless steel by hot-wire chemical vapor deposition (HWCVD) to gain insight into the effect of negative substrate bias on crystallization. Structural characterization of the silicon films was performed by Raman spectroscopy, x-ray diffraction, and scanning electron microscopy. It was found that the crystallinity of the films is obviously improved by applying the substrate bias, especially for films on stainless steel. At hot-wire temperature of 1800°C and negative substrate bias of ?800 V, grain size as large as 200 nm was obtained on stainless-steel substrate with crystalline fraction 9% higher than that of films deposited on glass and 15% higher than that of films deposited without substrate bias. It is deduced that the improvement of the crystallinity is mainly related to the accelerated electrons emitted from the hot wires. The differences in this improvement between different substrates are caused by the different electrical potential of the substrates. A solar cell fabricated by HWCVD with ?800 V substrate bias is demonstrated, showing an obviously higher conversion efficiency than that without substrate bias.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

基于MBE替代硅衬底的材料综述

主要介绍了几种用MBE技术生长HgCdTe/CdTe的Si衬底的替代性衬底材料的基本参数,以及不同材料的最新生长过程及结果,和对它们的生长结果的比较分析,以此来选择较为适合替代Si衬底来生长HgCdTe/CdTe的衬底。本文通过一系列的对比,得出目前最有发展前景的替代衬底是GaSb衬底,是未来发展的方向。     

功率HIC基板及其工艺布局设计研究

基板选用和工艺布局是功率混合集成电路两项重要技术内容。根据基板材料不同，功率基板及其布线工艺主要分为陶瓷基板和金属基板两大类。常规陶瓷基板以96％Al2O3陶瓷为代表，高导热陶瓷基板以BeO、AIN陶瓷为代表。陶瓷功率基板大部分采用厚膜布线工艺，另一种布线方式是DBC布线。绝缘金属基板的种类很多，最常使用的是铝基板，另...     

IC封装无芯基板的发展与制造研究

手持电子产品的薄型化催生了IC封装无芯基板,它不仅比IC封装有芯基板更薄,而且电气性能更加优越。介绍了IC封装无芯基板的发展趋势和制造中面临的问题。IC封装无芯基板以半加成法制造,翘曲是目前制程中的首要问题。翘曲改善主要依靠改变绝缘层材料和积层结构,可用云纹干涉法进行量测,并以模拟为指导加快开发周期。     

Investigation of the role of charged species in hot filament assisted CVD of diamond

Low pressure formation of diamond is well known, and has been accomplished by activating hydrocarbon/hydrogen mixtures near a heated substrate by means of a hot filament, dc glow discharge, etc. Many researchers have reported that externally applied voltages strongly affect the CVD process, and this is often attributed to electron bombardment effects. For this work, a filament assisted CVD reactor was modified by placing a grid between the filament and substrate, enabling independent control of the substrate potential and the filament to substrate current. Growth experiments under various bias conditions indicate that negatively charged species participate in the growth process, and that the reaction rate depends on the substrate potential. The growth rate becomes negligible when the substrate is held at a negative potential, even in the presence of a large current, which calls into question the electron bombardment explanation of the growth rate dependence on electrical bias.     

纺织基底无芯片RFID 湿度传感器

研制了一种无湿敏材料的纺织基底无芯片RFID 湿度传感器用于检测环境湿度。通过射频仿真软件 HFSS,获得谐振频率在2. 45 GHz 具有较高品质因数的纺织基底谐振器模型,对以谐振频率偏移量作为灵敏度指标 的检测原理进行了仿真。利用丝网印刷工艺和刻绘工艺分别在不同类型纺织物上制作了无芯片RFID 湿度传感器, 系统研究了制作工艺、纺织品类型和厚度对传感器湿敏特性的影响。结果表明,0. 5 mm 厚度下不同基底类型湿度传 感器的灵敏度由高至低依次为:棉基底、亚麻基底、聚酯纤维基底,恢复特性呈相反顺序,其中棉基底传感器在高湿 范围内平均灵敏度达3. 8 MHz/ %RH,聚酯纤维基底传感器恢复度达86%;相同类型的棉纺织基底下基底厚度越大, 平均湿度灵敏度越高,恢复特性越差。传感器稳定性测试表明传感器具有较好的中长期稳定性。对纺织基底湿度 传感器的感湿机理进行了分析,纺织纤维中的亲水基团与水分子间形成氢键,改变了基底的介电参数,传感器的湿 敏特性与组成纺织品的纤维成分、纤维细度、编织方式有关。     

重掺InP生长的InGaAs外延层迁移率的测量

通过衬底剥离技术对以重掺N型磷化铟(N+-InP)衬底生长的In0.53Ga0.47As外延层的迁移率测量方法进行了研究。首先,采用环氧树脂胶将In0.53Ga0.47As外延层粘贴在半绝缘蓝宝石衬底上,以盐酸溶液腐蚀掉InP衬底;之后,采用扫描电子显微镜能谱及金相显微镜对InP衬底的剥离情况及In0.53Ga0.47As薄膜的损伤情况进行了检测;最后采用范德堡法对粘贴在半绝缘蓝宝石衬底上的In0.53Ga0.47As薄膜的迁移率进行了测量。通过对比试验得出,剥离InP衬底的In0.53Ga0.47As薄膜的迁移率测量结果与理论值符合较好,与真值偏差在20%以内。     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

Selectively oxidized GaAs MESFETs transferred to a Si substrate

A novel method to electrically isolate grafted integrated GaAs devices from a conductive host substrate is demonstrated. An array of GaAs MESFETs is fabricated on a GaAs substrate and transferred to a Si substrate using a substrate removal process. The MESFETs contain a buried oxide layer under the channel region of each transistor that is formed by the thermal oxidation of AlAs. The purpose of this oxide layer is to provide electrical isolation from the conductive host substrate. Electrical evaluations are performed that show the transistors are fully functional after the oxidation and transfer processes and that the buried oxide does provide electrical isolation from the conductive host substrate