高频控制开关用沟槽MOSFET的研究

高频控制开关用功率器件要同时具备极低的导通电阻和栅漏电荷值,从而降低导通损耗和开关损耗.基于器件与工艺模拟软件TsupremⅣ和Medici,研究了工艺参数和设计参数对沟槽MOSFET器件击穿电压、比导通电阻和栅漏电荷的影响,优化设计了耐压30 V的开关用沟槽MOSFET器件.对栅极充电曲线中平台段变倾斜的现象,运用沟道长度调制效应给出了解释.     

碳化硅MOSFET开关瞬态模型

在碳化硅MOSFET大范围应用下,其开关瞬态过程愈发引人关注.由于碳化硅比起硅器件有更高的开关频率,因此其开关特性受到结电容和杂散电感的影响.对碳化硅MOSFET开关过程进行瞬态分析,推导了它的开关模型.通过开关模型提取出其电压变化率和电流变化率,在考虑杂散参数的基础之上寻找其与电压及电流变化率之间的联系.仿真及实验通...     

SiC MOSFET驱动与保护电路设计

介绍了SiC MOSFET驱动电路的设计要求,基于ACPL-355JC光耦驱动模块设计了SiC MOSFET驱动和保护电路。该电路具有驱动能力强、响应迅速和多种保护等优势。另外,针对SiC MOSFET开关过程中存在的瞬态电压尖峰和振荡问题,分析了SiC MOSFET开关过程中产生过电压和振荡的机理,并在此基础上提出一种RC吸收电路参数的计算方法。实验结果表明利用该方法设计的RC吸收电路能够有效解决SiC MOSFET在开关过程中的过电压和振荡问题﹐从硬件电路上有效降低开关噪声,从而保护功率器件。     

栅极电阻对GaN MOSFET瞬态特性的影响研究

为了研究栅极电阻对GaN MOSFET的开关速率和输出特性中出现振荡的影响,首先利用MOSFET的基本公式对其导通和关断时的输出瞬态电流进行了理论推导,然后通过实验平台测试GaN MOSFET的瞬态电流值,且与理论值对比,验证栅极电阻带来的影响。实验结果表明,GaN MOSFET的瞬态电流值实验值与理论值基本吻合,在导通和关断时,GaN MOSFET的输出瞬态电流和输出电流的高频震荡均随栅极电阻的增加而减小。栅极电阻从10 Ω变化到100 Ω时,导通时开关速率上升率占总开关速率上升率的84.7%,关断时开关速率下降率占总开关速率下降率的54.06%。在栅极电阻为10~100 Ω范围内,GaN MOSFET具有较快的开关速度。     

用于高效DC/DC变换器的沟槽MOSFET

面对市场对高效率电源的需求,工程师们无不急切期盼快速开关、低rDS(on)的功率MOSFET能有新进展。如今,一种新颖的厚底层氧化物工艺可以让Crss减小为栅极结构器件相应参数的一半,从而大大减少了器件导通所需的栅电荷,缩短了功率MOSFET的开关瞬态过程,同时让导通电阻保持在一个极低的水平上。这一技术对DC/DC变换器来说,意味着电路工作效率将得以提高。     

MOSFET的损耗分析与工程近似计算

根据MOSFET的简化模型,分析了导通损耗和开关损耗,通过典型的修正系数,修正了简化模型的极间电容。通过开关磁铁电源的实例计算了工况下MOSFET的功率损耗,计算结果表明该电源中工况下的MOSFET功率损耗比较小,可以长时间可靠稳定的工作。     

基于漏极导通区特性理解MOSFET开关过程

本文先介绍了基于功率MOSFET的栅极电荷特性的开关过程;然后介绍了一种更直观明析的理解功率MOSFET开关过程的方法:基于功率MOSFET的导通区特性的开关过程,并详细阐述了其开关过程.开关过程中,功率MOSFET动态的经过是关断区、恒流区和可变电阻区的过程.在跨越恒流区时,功率MOSFET漏极的电流和栅极电压以跨导为正比例系列,线性增加.米勒平台区对应着最大的负载电流.可变电阻区功率MOSFET漏极减小到额定的值.     

低压沟槽功率MOSFET导通电阻的最优化设计

研究了低压沟槽功率MOSFET(<100V)在不同耐压下导通电阻最优化设计的差别。给出了确定不同耐压MOSFET参数的方法,简要分析了沟槽MOSFET的导通电阻;利用Sentaurus软件对器件的电性能进行模拟仿真。理论和仿真结果均表明,耐压高的沟槽MOSFET的导通电阻比耐压低的沟槽MOSFET更接近理想导通电阻,并且,最优导通电阻和最优沟槽宽度随着耐压的提高而逐渐增大。     

实际应用条件下Power MOSFET开关特性研究(上)

针对实际应用中Power MOSFET开关工作状况与现有文献的描述有很大不同,使用不当易造成器件的损坏和设备的崩溃这一现象,在应用条件下对Power MOSFET开关特性进行了研究,深入分析了Power MOSFET的开关过程,提出了关于开关过程四阶段的新观点,并采用对开关过程的等效输入电容进行分段线性化的新方法对不同阶段的开关参数进行了计算,搭建了开关特性实验电路,实验结果表明,提出的Power MOSFET开关过程四阶段的新观点是正确的,等效输入电容分段线性化的新方法是合理的。     

实际应用条件下Power MOSFET开关特性研究(下)

从功率MOSFET内部结构和极间电容的电压依赖关系出发,对功率MOSFET的开关现象及其原因进行了较深入分析。从实际应用的角度,对功率MOSFET开关过程的功率损耗和所需驱动功率进行了研究,提出了有关参数的计算方法,并对多种因素对开关特性的影响效果进行了实验研究,所得出的结论对于功率MOSFET的正确运用和设计合理的MOSFET驱动电路具有指导意义。     

Study on the device characteristics of a quasi-SOI power MOSFETfabricated by reversed silicon wafer direct bonding

The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments     

Study of Dopant Redistribution at the Substrate-Source/Drain p-n Junction of Nanoscale MOSFET During Progressive Breakdown

During the evolution of dielectric breakdown (BD) in MOSFETs, the substantial localized temperatures (which could exceed the silicon melting point) in the vicinity of the BD spot may cause dopants at the source/drain (S/D) to be redistributed (IEDM Tech. Dig., p. 717, 2004; IEEE Proc. IPFA, p. 131, 2005). The preliminary study of dopant redistribution based on the diode current-voltage (I-V) characteristics at the substrate-S/D p-n junction of a BD MOSFET was presented by Lim (IEEE Proc. IPFA, p. 131, 2005). The post-BD MOSFET diode current measured in the reverse bias as well as the low-voltage region of the forward bias was found to increase significantly as progressive BD evolves. The simulation results associated with the dopant redistribution are in good agreement with the experimental measurements. This confirms that the dopant redistribution is one of the dominant mechanisms responsible for the change in the post-BD MOSFET diode I-V characteristics. In addition, the dopant redistribution in a large-area long-channel BD MOSFET is found to be a function of BD location. However, the BD location dependence of the dopant redistribution will vanish in a "narrow" short-channel BD MOSFET     

适于器件及电路分析的全耗尽短沟道LDD／LDSSOI MOSFET器件模型

本文系统描述了全耗尽短沟道ＬＤＤ／ＬＤＳＳＯＩＭＯＳＦＥＴ器件模型的电压电压特性。该模型扩展了我们原有的薄膜全耗尽ＳＯＩＭＯＳＦＥＴ模型，文中着重分析了器件进入饱和区后出现的沟道长度调制效应，及由于ＬＤＤ／ＬＤＳ区的存在对本征ＭＯＳ器件电流特性的影响。     

The temperature dependence of threshold voltages in submicrometer CMOS

The temperature coefficient of the threshold voltage in long buried-p-channel MOSFET isdV_{th}/dT = 2.02mV/°C, which is much larger than that in the long enhancement-mode n-channel MOSFET (-1.27 mV/°C). The difference is caused by the charge freeze-out phenomenon in the buried-channel MOSFET. The absolute value of the temperature coefficient of the threshold voltage|dV_{th}/dT|, decreases with decreasing channel length in the n-channel MOSFET, however, it increases with decreasing channel length in the submicrometer p-channel MOSFET. The difference results from the majority-carrier spill-over phenomenon in the buried-p-channel MOSFET.     

基于MOSFET的半导体激光器驱动电路设计及其改进

在金属氧化物半导体场效应晶体管(MOSFET)作为开关配合电容充放电实现脉冲功率放大时,输出的脉冲电流受到MOSFET元件性能制约,而且由于分布参数的影响脉冲电流非常容易出现过冲。为了解决这些问题,提出了一种MOSFET互补输出电路,它能提供更快的脉冲关断时间,并且对过冲的产生起到一定抑制作用。经实验证明,改进后电路的输出得到了改善。     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.     

“Square Root Domain” Filter Design and Performance

This paper discusses the implementation and performance of square root domain filters, which can be considered as the CMOS equivalent of the bipolar log domain technique. The square root design methodology is based on exploiting the MOSFET large-signal square law characteristic to implement filters which are input-output linear, but operate with internally non-linear signals. The design of subcircuits required for the implementation of square root domain filters is described based on the MOSFET translinear principle, and various performance issues are discussed. Simulation and measured results are also presented to confirm the validity of this approach, which may be attractive for low-voltage operation at frequencies in the MHz range.     

MOSFET的驱动保护电路的设计与应用

率场效应晶体管由于具有诸多优点而得到广泛的应用;但它承受短时过载的能力较弱,使其应用受到一定的限制。分析了MOSFET器件驱动与保护电路的设计要求;计算了MOSFET驱动器的功耗及MOSFET驱动器与MOS-FET的匹配;设计了基于IR2130驱动模块的MOSFET驱动保护电路。该电路具有结构简单,实用性强,响应速度快等特点。在驱动无刷直流电机的应用中证明,该电路驱动能力及保护功能效果良好。     

SiC MOSFET栅极驱动电路研究综述

凭借碳化硅(SiC)材料的宽禁带、高击穿电场、高电子饱和速率和高导热性等优点,SiC MOSFET广泛应用在高压、高频等大功率场合。传统基于硅(Si)MOSFET的驱动电路无法完全发挥SiC MOSFET的优异性能,针对SiC MOSFET的应用有必要采用合适的栅驱动设计技术。目前,已经有很多学者在该领域中有一定的研究基础,为SiC MOSFET驱动电路的设计提供了参考。对现有基于SiC MOSFET的PCB板级设计技术进行了详细说明,并从开关速度、电磁干扰噪声以及能量损耗等方面对其进行了总结和分析,给出了针对SiC MOSFET驱动电路的设计考虑和建议。     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs