A high-order curvature compensation technique for bandgap voltage reference using subthreshold MOSFETs

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.     

0.75 V supply nanowatt resistorless sub-bandgap curvature-compensated CMOS voltage reference

This work presents a resistorless self-biased and small area sub-bandgap voltage reference that works in the nano-ampere consumption range with 0.75 V of power supply. The circuit applies a curvature compensation technique that allows an extended temperature range without compromising the temperature stability. The behavior of the circuit is analytically described, and a design methodology is proposed which allows the separate adjustment of the bipolar junction transistor bias current and its curvature compensation. Simulation results are presented for a 180 nm CMOS process, where a reference voltage of 469 mV is designed, with a temperature coefficient of 5 ppm/°C for the ?40 to 125 °C extended temperature range. The power consumption of the whole circuit is 16.3 nW under a 0.75 V power supply at 27 °C. The estimated silicon area is 0.0053 mm².     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.     

Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS

Portable and implantable device applications require low supply voltage reference circuits due to increasing trend for lower power requirements. Voltage references have been proposed for operation below 1 V for CMOS and a comprehensive analysis of the behavior of the different topologies is needed for ultra-low power designs, in order to select the right circuit topology for a given requirement. This work compares two major classes of voltage reference topologies: threshold voltage (V_T0)-based and (V_G0) bandgap voltage-based reference circuits. Four different topologies of voltage-reference designs with 1-V supply were designed and fabricated in 130 nm CMOS process. Monte Carlo analysis shows the variability of the references and of their temperature coefficients (TC), and the results are compared to measured samples. Simulations and measurements show that the threshold voltage-based references are more susceptible to the variations in the CMOS fabrication process.     

A low power CMOS voltage reference generator with temperature and process compensation

A low power CMOS voltage reference with process compensation is presented in TSMC 0.18-μm standard CMOS technology. Detailed analysis of the process compensation technique is discussed. The circuit is simulated with Spectre. Simulation results show that, without any trimming procedure, the output voltage achieves a maximum deviation of 0.35 % across different process corners. The temperature coefficient of the proposed circuit is 12.7 ppm/°C in a temperature range from ?40 to 85 °C and the line sensitivity is 0.036 mV/V with a supply voltage range from 1.2 to 2.5 V under typical condition. The maximum supply current is 390.4 nA at maximum supply voltage and ?40 °C. The power supply rejection ratio is ?68.3 dB at 100 Hz and 2.5 V without any filtering capacitor.     

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10^?6/°C when temperature is changed from ?40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of ?104.54 dB, ?104.54 dB, ?104.5 dB, ?101.82 dB and ?79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.     

Design and implementation of all MOS micro-power voltage reference circuit

In this work we are proposing the all MOST based reference voltage generating circuit, which utilizes the classical principle of addition of two voltages with opposite temperature coefficients. The targeted application of the proposed circuit is a low-dropout regulator which is used in a RF energy harvesting system. The proposed voltage reference circuit is implemented using a standard 0.18 μm CMOS technology. It generates the average reference voltage of 543.658 mV with an average temperature coefficient of 17.43 ppm/°C in the temperature range of ?40 to +85 °C, for the operating supply voltage ranging from 1.25 to 2 V. The maximum power consumption of the proposed architecture is ≈1.5 μW, including power dissipation in bias circuitry and the reference voltage generating core at 2 V supply voltage. The averaged measured line regulation is 1.642 mV/V. The measured power-supply rejection ratio without any filtering capacitor at 100 Hz and 1 MHz are ?62.24 and ?18.94 dB, respectively. Additionally, the measured noise density without any filtering capacitor at 10 Hz and 100 KHz is 20.54 and \(0.30\,\upmu \hbox {V}/\sqrt{\hbox{Hz}}\) , respectively. The proposed circuit has silicon area of ≈0.007 mm².     

A 0.003-mm2, 0.35-V, 82-pJ/conversion ultra-low power CMOS all digital temperature sensor for on-die thermal management

In this paper, a 0.35 V, 82 pJ/conversion ring oscillator based ultra-low power CMOS all digital temperature sensor is presented for on-die thermal management. We utilize subthreshold circuit operation to reduce power and adopt an all-digital architecture, consisting of only standard digital gates. Additionally, a linearization technique is proposed to correct the nonlinear characteristics of subthreshold MOSFETs. A bulk-driven 1-bit gated digitally controlled oscillator is designed for the temperature sensing node. Also, a 1-bit time-to-digital converter is employed in order to double the fine effective resolution of the sensor. The proposed digital temperature sensor has been designed in a 90-nm regular V _T CMOS process. After a two-point calibration, the sensor has a maximum error of ?0.68 to +0.61 °C over the operating temperature range from 0 to 100 °C, while the effective resolution reaches 0.069 °C/LSB. Under a supply voltage of 0.35 V, the power dissipation is only 820 nW with the conversion rate of 10K samples/s at room temperature. Also, the sensor occupies a small area of 0.003 mm².     

A programmable voltage reference optimized for power management applications

A 3-bits programmable, low drift, high PSRR and high precision voltage reference, optimized for Power Management (PM) applications, is presented. The topology is based on a high-performance bandgap voltage reference that presents a PSRR of up to 80 dB, which is required in PM applications, because they employ mixed-signal circuits, where high frequency switching noise is present. The proposed approach was successfully verified in a standard 0.35 μm CMOS process. The experimental results confirmed that, for power supply between 3.0 and 3.3 V, and temperatures in ?20°C to 80°C range, the programmable output voltage V _REF exhibits a worst case precision of ±3%.     

A novel sub-1V bandgap reference with offset compensated techniques

A sub-1V bandgap reference (BGR) featuring with low offset is proposed. In order to reduce the effect of the offset of the operation amplifiers, the proposed BGR introduces feedback paths to not only realize sub-1V output but also reduce the factor of operation amplifier’s offset voltage. In addition, a cross-coupled structure is dedicated to reduce the offset voltage factor further by increasing the bipolar junction transistor’s base emitter voltage difference. The new proposed offset-compensated BGR has been successfully verified in a 0.5 μm BCD process. The relative accuracy is increased by 4 times compared with the conventional circuit. Furthermore, the proposed circuit achieves a temperature coefficient of 8.5 ppm/°C over a wide temperature range of ?20 to 120 °C, power supply rejection ratio of more than 70 dB at low frequencies and a line regulation of 0.09 % easily, without requiring additional operational amplifiers or complex circuits.     

A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology

A low power voltage reference generator operating with a supply voltage ranging from 1.6 to 3.6?V has been implemented in a 90-nm standard CMOS technology. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6?V and at 125°C is 173?nA. It provides a 771?mV voltage reference. A temperature coefficient of 7.5?ppm/°C is achieved at best and 39.5?ppm/°C on average, in a range from ?40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. Several process parameters affect the performance of the proposed voltage reference circuit, so a process adjustment aimed at correcting errors in the reference voltage caused by these variations is dealt with. The total block area is 0.03?mm².     

A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage

In this work a low power consumption reference voltage in commercial 40 nm technology is proposed. It adopts a new approach to produce a temperature invariant reference voltage for outdoor RFID applications. To do so, the positive temperature coefficient (TC) of the produced output voltage of a Dickson charge pump is used to cancel out the negative temperature coefficient of the threshold voltage (V_th) of CMOS devices. The result is, according to the post-layout Cadence simulation, a 1.224 V reference voltage with a TC of 60 ppm°C⁻¹ in the temperature range of −10 ^°C to 125 ^°C. The circuit consumes 7 nW with an active area of 0.00033 mm².     

非制冷红外焦平面读出电路用带隙基准电压源

提出了一种高精度、低功耗、小面积的电流型CMOS基准电压源以满足非制冷红外焦平面(IRFPA)读出电路对基准电压源模块的要求。设计中采用两种分别具有正负一阶温度系数的电阻,通过对基准电压源的高阶温度系数进行补偿,获得更好的温度系数TC(Temperature Coefficient)。通过使用共源共栅结构代替传统的运放,节约了传统运放和偏置电路的功耗,并且具有出色的电源电压抑制比PSRR(Power Supply Reject Ratio)。该设计使用标准0.18 m CMOS工艺实现,工作电压3.3 V,-40~120 ℃温度范围内,输出基准电压温度系数约为3.7 ppm/℃,PSRR约为-78 dB@1 kHz,在25 ℃时消耗电流6.3 A,消耗芯片面积仅230 m100 m,所提出的电路是一种低功耗、节约面积的设计。     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

A 3 V 110 μW 3.1 ppm/°C curvature-compensated CMOS bandgap reference

This paper presents design of a high-precision curvature-compensated bandgap reference (BGR) circuit implemented in a 0.35 μm CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves the lowest reported temperature coefficient of ~3.1 ppm/°C over a wide temperature range of [?20°C/+100°C] after trimming, a power supply rejection ratio of ?80 dB at 1 kHz and an output noise level of 1.43 μV $ \sqrt {\text{Hz}} $ at 1 kHz. The BGR circuit consumes a very low current of 37 μA at 3 V and works for a power supply down to 1.5 V. The BGR circuit has a die size of 980 μm × 830 μm.     

A low-voltage,versatile CMOS four-quadrant analogue multiplier

This paper describes a four-quadrant analogue multiplier circuit using a low-voltage power supply. It comprises two voltage/current adders and a basic multiplier. Its major advantages over other low-voltage multipliers are that it can operate on either a single power supply or two power supplies, and that its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects were analysed and the simulated results revealed that: (1) for a two-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.4?mW and the ?3?dB bandwidth is more than 55?MHz; (2) for a single-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.2?mW and the ?3?dB bandwidth is more than 55?MHz. Experimental results are provided to confirm the operation of the circuit.     

Frequency multiplier using pulse-width control loop

A frequency multiplier circuit based on a well-known pulse-width control loop is presented. The proposed circuit can be used to enhance the output frequency range of a phase-locked loop (PLL) by using multiple phases of the voltage-controlled oscillator. It can be used for enhancing the output frequency range of new as well as existing PLL designs with minimum impact on PLL loop dynamics. The circuit is generic in nature and can be used with any multi-phase oscillator type. The circuit is designed in 65 nm complimentary metal oxide semiconductor (CMOS) technology and has been simulated across process, voltage and temperature (PVT) corners with temperature variation from ?40°C to 125°C, analogue supply voltage variation from 1.62 V to 1.98 V, and digital supply voltage variation from 1.1 V to 1.3 V.     

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8  nW at 0.6 V supply. The active area is 0.019 mm².     

指数型温度补偿BiCMOS带隙基准电压源设计

利用双极型管电流增益的温度特性,采用UMC0.6μm BiCMOS工艺设计了一款指数型温度补偿BiCMOS带隙基准电压源。测试结果表明:温度在10°C～100°C之间变化,带隙基准电压随温度变化最大偏移为2.5mV;电源电压在2.5～5.0V之间变化,带隙基准电压随电源电压直流变化最大偏移为0.95mV。该带隙基准电压具有较高的温度稳定性和电压稳定性。     

A CMOS piecewise curvature-compensated voltage reference

This paper presents a novel approach to the design of a high-precision CMOS voltage reference. The proposed circuit utilizes MOS transistors instead of bipolar transistors to generate positive and negative temperature coefficient (TC) currents summed up to a resistive load to generate low TC reference voltage. A piecewise curvature-compensation technique is also used to reduce the TC of the reference voltage within a wider temperature range. The output reference voltage can be adjusted in a wide range according to different system requirements by setting different parameters such as resistors and transistor aspect ratios. The proposed circuit is designed for TSMC 0.6 μm standard CMOS process. Spectre-based simulations demonstrate that the TC of the reference voltage is 4.3 ppm/°C with compensation compared with 107 ppm/°C without compensation in the temperature ranges from −15 to 95 °C using a 1.5 V supply voltage.