High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

Two-step V<Subscript>cm</Subscript>-based MS switching method with dual-capacitive arrays for SAR ADCs

An ultra-low-power two-step merge and split (MS) switching method for a dual-capacitive arrays (DCAs) successive approximation register analogue-to-digital converter is presented. This method only requires two reference levels, i.e. Gnd and V_cm (V_cm = 1/2V_ref). Compared with the conventional method, the proposed method achieves 99.89 and 80.96% reduction in average switching energy and capacitors, respectively, meanwhile maintaining good linearity. In addition, it barely consumes reset energy and keeps common-mode voltage of DCAs almost constant.     

利SAR ADC降低成本、扩展应用

在解决如何让特定应用和ADC体系结构相互匹配这一问题上,工业界已经推出了一种称为SAR(Successive Approximation Register,连续逼近寄存器)ADC的数模转换产品,它可以被看作是∑-△和流水线式ADC折衷的产物.     

An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

Configurable array of low-complex SAR ADCs

An array of low-complex SAR ADCs, configurable in time-interleaved (TI) or parallel modes to reach 1 GS/s or to serve multiple inputs at hundreds of MS/s, is proposed in this letter. Each SAR ADC channel exploits a threshold-configuring scheme, to avoid internal DAC thus saving circuit complexity, plus a dynamic comparator which allows for power consumption scalable versus processing speed. Implementation results in 90 nm 1 V CMOS technology are presented and compared to the state of the art.     

A code-pattern-driven digital background calibration technique for SAR ADCs

The article presents the buck converter for the application on headlights of vehicle with chip-level design. The LED components are used as for lighting source, which near/far lights are controlled with high-current switching circuit in the chip. The level-shift circuit and its current driver is proposed to control the input of high-voltage power MOS. The bypass method is presented to reduce the transient time as load current changes suddenly. The input voltage widely ranges from 8 to 21 V while keeping a stable output voltage with 6 V. The chip current can output from 20 to 1500 mA with excellent regulation. This chip had been implemented with TSMC0.25 µm HV- process, and the size of the circuit layout is about 8.6 mm², where includes power switch and far/near lighting switches. Measurements show that peak efficiency can achieve 86.3%. The power regulation is excellent, where the load regulation is only 0.3%, and the line regulation is only 0.5%.

     

Design of low-power SAR ADCs using hybrid DACs

In the past decade, successive approximation register (SAR) analog-to-digital converter (ADC) has become a popular topology in a wide range of resolutions and sampling rates. This paper investigates methods to improve the energy-and-area efficiency of the SAR ADCs by focusing on the design of the internal digital-to-analog converter (DAC). Different hybrid resistive–capacitive DACs are studied in detail. It is shown that more than an order of magnitude improvement in energy efficiency of the DAC is achievable. The conditions for such an improvement are discussed.     

High energy-efficient partial floating capacitor array DAC scheme for SAR ADCs

A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. The proposed method can achieve high energy savings and high linearity due to the fact that the partial floating and split capacitor techniques are combined. This scheme has no reset energy consumption, and achieves purely 98.63% less switching energy and 75% reduction of the total capacitance over the conventional switching scheme. Moreover, the proposed scheme achieves Differential Nonlinearity and Integral Nonlinearity only 0.140LSB and 0.122LSB, respectively.     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

Single event transient effects on charge redistribution SAR ADCs

This work presents a study on the effects of Single Event Transients on Successive Approximation Register Analog-To-Digital Converters (ADC) based on charge redistribution. The effects of SETs are analyzed by means of an extensive fault injection campaign by using a SPICE simulator and a predictive 130nm CMOS technology model. Faults are injected in the analog blocks and in the digital control circuit of the converter. Results show that the transient effects may change the state of one or more bits of conversion, since the affected conversion stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Results also allow to identify the most sensitive nodes and the failure mechanisms associated to transient effects on this type of converter. Finally, some design-level mitigation strategies are applied, in a way that the error rate and the magnitude of conversion errors are significantly reduced.     

Energy-efficient switching scheme for SAR ADC with only two reference voltages

An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter.The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.     

高速度、低功耗和真正同时采样的SAR ADC

对于从几Hz到几MHz模拟信号的快速数字化,逐次逼近型（SAR）ADC是很多应用的最佳选择。SARADC的快速响应和低延迟使其非常适用于单通道或多通道的数据采集。低功率SARADC至关重要,因为越来越多的设计开始采用较低的电源电压和较严格的功率预算。就需要单个输入信号的设计师来说,解决方案尺寸也是一个关键要求,     

机载斜视聚束合成孔径雷达快速成像算法

极坐标格式算法(PFA)是传统聚束SAR的经典成像算法,但用于斜视聚束成像存在二维频域插值计算量巨大、插值精度受插值核函数长度制约以及最终图像旋转带来成像质量下降等问题。针对上述问题,文中提出一种基于尺度变化的快速PFA算法,不仅能避免斜视成像后的图像旋转操作,还具有计算效率高的优势。快速PFA算法只需要FFT和复乘运算即可完成,与直接插值PFA算法相比计算量降低到原来的30%~50%。仿真实验验证了文中方法的有效性。     

Simple algorithm for soil moisture retrieval with co-polarized SAR data

In this paper, an empirical methodology to retrieve bare soil moisture by Synthetic Aperture Radar (SAR) is developed. The model is based on Advanced Integral Equation Model (AIEM). Since AIEM cannot express cross-polarized backscattering coefficients accurately, we propose an empirical model to retrieve soil moisture for bare farmland only with co-polarized SAR data. The soil moisture can be obtained by solving an equation of HH and VV polarized data without any field measurements. Both simulated and real SAR data are used to validate the accuracy of the model. This method is especially effective in a large area where the surface roughness is difficult to be completely measured.     

Genetic algorithm for routing switching units

A hybrid model is presented of a genetic algorithm for routing switching units using fuzzy logic in genetic operators. A fuzzy objective function is used to take into account the criteria of the problem. The algorithm has been developed with regard to various physical effects during routing, thereby reducing the design time of devices by eliminating the need for rerouting after the verification stage.