High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

Two-step V<Subscript>cm</Subscript>-based MS switching method with dual-capacitive arrays for SAR ADCs

An ultra-low-power two-step merge and split (MS) switching method for a dual-capacitive arrays (DCAs) successive approximation register analogue-to-digital converter is presented. This method only requires two reference levels, i.e. Gnd and V_cm (V_cm = 1/2V_ref). Compared with the conventional method, the proposed method achieves 99.89 and 80.96% reduction in average switching energy and capacitors, respectively, meanwhile maintaining good linearity. In addition, it barely consumes reset energy and keeps common-mode voltage of DCAs almost constant.     

利SAR ADC降低成本、扩展应用

在解决如何让特定应用和ADC体系结构相互匹配这一问题上,工业界已经推出了一种称为SAR(Successive Approximation Register,连续逼近寄存器)ADC的数模转换产品,它可以被看作是∑-△和流水线式ADC折衷的产物.     

An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.     

Error suppression techniques for energy-efficient high-resolution SAR ADCs

The successive approximation register (SAR) is one of the most energy-efficient analog-to-digital converter (ADC) architecture for medium-resolution applications. However, its high energy efficiency quickly diminishes when the target resolution increases. This is because a SAR ADC suffers from several major error source, including the sampling kT/C noise, the comparator noise, and the DAC mismatch. These errors are increasing hard to address in high-resolution SAR ADCs. This paper reviews recent advances on error suppression techniques for SAR ADCs, including the sampling kT/C noise reduction, the noise-shaping (NS) SAR, and the mismatch error shaping (MES). These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency.     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

ABSTRACT

A new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).     

A code-pattern-driven digital background calibration technique for SAR ADCs

The article presents the buck converter for the application on headlights of vehicle with chip-level design. The LED components are used as for lighting source, which near/far lights are controlled with high-current switching circuit in the chip. The level-shift circuit and its current driver is proposed to control the input of high-voltage power MOS. The bypass method is presented to reduce the transient time as load current changes suddenly. The input voltage widely ranges from 8 to 21 V while keeping a stable output voltage with 6 V. The chip current can output from 20 to 1500 mA with excellent regulation. This chip had been implemented with TSMC0.25 µm HV- process, and the size of the circuit layout is about 8.6 mm², where includes power switch and far/near lighting switches. Measurements show that peak efficiency can achieve 86.3%. The power regulation is excellent, where the load regulation is only 0.3%, and the line regulation is only 0.5%.

     

Design of low-power SAR ADCs using hybrid DACs

In the past decade, successive approximation register (SAR) analog-to-digital converter (ADC) has become a popular topology in a wide range of resolutions and sampling rates. This paper investigates methods to improve the energy-and-area efficiency of the SAR ADCs by focusing on the design of the internal digital-to-analog converter (DAC). Different hybrid resistive–capacitive DACs are studied in detail. It is shown that more than an order of magnitude improvement in energy efficiency of the DAC is achievable. The conditions for such an improvement are discussed.     

一种用于SAR ADC开关电容比较器的失调消除技术

论文阐述了一种用于逐次逼近ADC开关电容比较器的失调消除技术。采用预放大加再生锁存的比较结构,基于0.18μm 1P5M CMOS工艺设计实现了一种伪差分比较器。通过采用前级预放大器输入失调消除技术以及低失调再生锁存技术进行设计,整个比较器的输入失调电压小于0.55mV。通过采用预放大加再生锁存的比较模式,整个比较器的功耗有效减小,不足0.09mW。在电源电压为1.8V、ADC采样速率为200kS/s、时钟频率为3MHz的情况下,比较器能达到13位的转换精度。最后,通过设计讨论、后仿真分析及其在一种10位200kS/s的触摸屏SAR ADC中的成功应用验证了本文比较器的实用性和优越性。     

High energy-efficient partial floating capacitor array DAC scheme for SAR ADCs

A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. The proposed method can achieve high energy savings and high linearity due to the fact that the partial floating and split capacitor techniques are combined. This scheme has no reset energy consumption, and achieves purely 98.63% less switching energy and 75% reduction of the total capacitance over the conventional switching scheme. Moreover, the proposed scheme achieves Differential Nonlinearity and Integral Nonlinearity only 0.140LSB and 0.122LSB, respectively.     

Single event transient effects on charge redistribution SAR ADCs

This work presents a study on the effects of Single Event Transients on Successive Approximation Register Analog-To-Digital Converters (ADC) based on charge redistribution. The effects of SETs are analyzed by means of an extensive fault injection campaign by using a SPICE simulator and a predictive 130nm CMOS technology model. Faults are injected in the analog blocks and in the digital control circuit of the converter. Results show that the transient effects may change the state of one or more bits of conversion, since the affected conversion stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Results also allow to identify the most sensitive nodes and the failure mechanisms associated to transient effects on this type of converter. Finally, some design-level mitigation strategies are applied, in a way that the error rate and the magnitude of conversion errors are significantly reduced.     

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10⁴ shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics.