共查询到17条相似文献,搜索用时 531 毫秒
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本文针对甚大规模集成电路的时延驱动布局问题提出了一个新的解决途径,其策略是将结群技术应用于二次规划布局过程中.结群的作用是可大幅度地降低布局部件的数量.本文设计了一个高效的结群算法CARGO,其优点是具有全局最优性并且运行速度很快.采用了一个基于路径的时延驱动二次规划布局算法对结群后的电路完成布局过程.由于二次规划布局算法能够在很短时间内寻找到全局最优解,故本文的算法更有希望彻底解决甚大规模电路的布局问题.在一组MCMC标准测试电路上对算法进行了测试,得到了满意的结果. 相似文献
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功耗和时延双重驱动的VLSI布局算法 总被引:3,自引:2,他引:1
针对超大规模的门阵列和标准单元电路,本文提出一种功耗和时延双重驱动的VLSI布局算法.以往发表的布局算法中,很少能够同时处理功耗和时延的双重约束.在以往的时延驱动布局算法中,仅有一个算法[3]能够处理超大规模的电路;该算法尚存在以下问题:1)其基本思想只能处理组合电路;2)延迟模型过于简单,因而不适合深亚微米工艺;3)该算法不是基于全路径的.我们的算法克服了这些问题,能够精确地控制最长路径延迟,同时保证优秀的布局质量和功耗的均匀分布.而且,对于超大规模的电路,我们的算法是同类算法中最快的. 相似文献
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本文针对门阵列和标准单元设计系统提出一种分级的时延驱动布局算法,以前的时延驱动布局算法除了文献[22]以外都不是分级的,因而运算时间很长,而且最长路径上的信号延迟达不到最优;而文献[22]的算法只能处理时序关系是DAG图(有向无环图)的电路,也就是说,电路中不能包含寄存器元件,本文的算法是适用于一般的电路.与RITUAL/Tiger系统比较,我们用比较短的运算时间得到了较小的信号延迟. 相似文献
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《中国无线电电子学文摘》2004,(5)
TN4 2004050515优化时延与拥挤度的增t式布局算法/李卓远,吴为民,洪先龙(清华大学)”半导体学报一2 004,25(2)一158一164提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%图3表3参15(木)的散射参数解析表达式,给出了… 相似文献
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Manohararajah V. Chiu G.R. Singh D.P. Brown S.D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):895-903
This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial field-programmable gate-array (FPGA) architectures were used in this paper. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Furthermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction. 相似文献
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Ke Cao Jiang Hu Mosong Cheng 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(12):1332-1340
As the VLSI feature size has already decreased below lithographic wavelength, the printability problem, due to strong diffraction effects, poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of resolution enhancement techniques (RET) can alleviate the printability problem but cannot reverse the trend of deterioration. Moreover, over-usage of RET may dramatically increase photo-mask cost and increase the cycle time for volume production. Thus, there is a strong demand to consider the subwavelength printability problem in circuit layout designs. However, layout printability optimization should not degrade circuit timing performance. In this paper, we introduce a wire sizing and spacing method to improve wire printability with minimal adverse impact on interconnect timing performance. A new printability model is proposed to handle partially coherent illuminations. The complex printability and timing optimization problem is solved in a two-phase approach. The difficulty of the printability optimization due to its multimodal nature is handled with a sensitivity-based heuristic. A coupling aware timing driven continuous wire sizing algorithm is also provided. Lithographic simulation results show that our approach can improve the printability in term of edge placement error (EPE) by 20%-40% without violating timing, wire width, and spacing constraints. 相似文献
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文章研究了在GaAs工艺,双层金属布线,基于门阵的宏元胞模式下,采用时间驱动算法布局设计(TimingDrivenPlacement)的布线算法,算法以芯片性能得到最大限度的改善,包括芯片关键路径时延最短,互连线总长最短,最长互连线最甜,布线密度均匀等为目标,从而达到超高速的目的。 相似文献
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针对宽带卫星通信系统中非整数倍采样的定时恢复问题,介绍了一种整数倍变换法—将非整数倍采样信号进行速率整数倍变换后再进行定时估计,并提出了一种新的定时恢复方法。这种新方法对采样数据直接进行定时估计,然后再内插出同步信号。通过对两种方法的分析比较可知,新方法的实现复杂度更低,定时恢复性能更好。 相似文献
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Qinghua Liu Bo Hu Marek-Sadowska M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(10):1004-1014
In this paper, we address the problem of individual wire-length prediction and demonstrate its usefulness in timing-driven placement. Many researchers have observed that different placement algorithms produce different individual wire lengths. We postulate that to obtain accurate results, individual wire-length prediction should be coupled with the placement flow. We embed the wire-length prediction into the clustering step of our fast placer implementation (FPI) framework . The predicted wire lengths act as constraints for the simulated annealing refinement stage, which guides the placement toward a solution fulfilling them. Experimental results show that our prediction process yields accurate results without loss of quality and incurs only a small cost in placement effort. We successfully apply the wire-length prediction technique to timing-driven placement. Our new slack assignment algorithm with predicted wire lengths (p-SLA) gives on average an 8% improvement in timing performance compared with the conventional modified zero-slack algorithm (m-ZSA). 相似文献
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Chao-Yang Yeh Marek-Sadowska M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(10):1028-1037
Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new linear programming formulation for timing-aware sequential budgeting, which guarantees that the clock period constraints are met. We demonstrate the usefulness of our approach in the context of field-programmable gate arrays placement flow. We have performed two experiments. The first experiment compares sequential budgeting with traditional budgeting and retiming. The results show that the new placement flow reduces budget violations by 16% and improves timing by 9%. In the second experiment, we demonstrate methods of interconnect length prediction that are useful to estimate delay and to decide net weighting in sequential budgeting. We compare net delay predictions using traditional delay budgeting, the Donath's method, and mutual contraction. The results from this experiment show that sequential budgeting, using the new net weighting and predicted delays, can improve circuit speeds on average by 12.29%, compared to traditional timing-driven placement. The new net weighting method also performs better than a uniform weighting method. 相似文献
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Rshdee Alhakim Kosai Raoof Emmanuel Simeu Youssef Serrestou 《Signal, Image and Video Processing》2013,7(4):741-757
Timing acquisition constitutes a major challenge in realizing ultra-wideband communications. In this paper, we propose the timing with dirty template (TDT) approach as a promising candidate for achieving rapid, accurate and low-complexity acquisition. We describe the dirty template (DT) technique, in order to develop and test timing algorithms in both modes: data-aided (DA) and non-data- aided (NDA) modes. First, we derive the Cramer–Rao lower bound, which is used as a fundamental performance limit for any timing estimator. Next, the TDT acquisition estimator is achieved by using the Maximum Likelihood concept. Then we propose a new method, based on Time-Hoping codes, to improve the performance estimation of the original dirty template algorithms. Simulation shows the estimation error results of the modified method in the DA and NDA modes. It confirms the high performance and fast timing acquisition of DA mode, compared with NDA mode, but with less bandwidth efficiency. 相似文献