Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators

The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.     

Deuterium passivation of interface traps in MOS devices

The mechanism for deuterium passivation of interface traps in MOS devices is studied. Normal channel hot electron (CHE) stress was performed on hydrogen-passivated devices to locally desorb hydrogen from the interface at the drain region. The stressed devices were annealed in deuterium at 400°C, resulting in a full recovery of device characteristics. These devices were then subjected to CHE stress again in two modes. Some of them were stressed in the normal mode while others were stressed in the reverse mode in which the source and drain were interchanged. Compared with hydrogenated devices, these deuterated devices under the normal stress exhibit a significant reduction in interface trap generation and threshold voltage shift. In contrast, insignificant reliability improvement was observed for the reverse stress case. The asymmetric degradation behaviors on these deuterated devices suggest that the effectiveness of implementing deuterium to improve device reliability is limited by its replacement of pre-existing hydrogen at the oxide/silicon interface     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

Enhanced degradation in polycrystalline silicon thin-filmtransistors under dynamic hot-carrier stress

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G_{m max}) in static stress, G_{m max} in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation     

Hot-Carrier Effects in Strained n-Channel Transistor With Silicon–Carbon (Si1 − yCy) Source/Drain Stressors and Its Orientation Dependence

We report the hot-carrier effects in a novel strained n-channel transistor (n-FET) featuring silicon-carbon source and drain (Si_1-yC_y S/D) stressors, and its dependence on channel orientations for the first time. Due to strain-induced bandgap reduction, Si_1-yC_y S/D n-FETs show enhanced impact ionization and therefore more pronounced drive current degradation over a control n-FET. As a consequence of the increased interface state generation, a strained n-FET with [010] channel shows worse hot-carrier reliability over a transistor with the conventional [110] channel, which leads to a larger shift in threshold voltage and subthreshold swing. In addition, a hot-carrier lifetime projection shows a dependence of operating drain voltage on the channel orientation of the strained n-FET.     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Spatially resolving the hot carrier degradations of poly-Si thin-film transistors using a novel test structure

A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HC) degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified.     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Importance of ballistic carriers for the dynamic response insub-100 nm MOSFETs

Monte-Carlo simulations of the metal-oxide semiconductor field-effect transistor (MOSFET) switch-off characteristics are used to verify that ballistic carriers change the electric-field distribution along the MOSFET channel below 100 nm channel length. The field change has two main aspects: increase of field magnitude and shift of zero-field position from channel middle to source side. The shift of the zero-field position forces more carriers to flow to drain during switch-off. This results in a changed charge-partitioning ratio Q_s (source)/Q_d (drain) for sub-100 nm MOSFETs from 60/40 (long channel) to 40/60 at 40 nm and a slower emptying of the channel during switch-off than expected from the channel length reduction     

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons     

An efficient method for characterizing time-evolutional interfacestate and its correlation with the device degradation in LDD n-MOSFETs

A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state N_it (x) and the device drain current degradation of submicron LDD n-MOSFETs. In this method, by making use of the conventional charge pumping measurement in combination with the power-law dependence of interface damages on stress time, the spatial distribution N_it(x) and the effective damaged length L_dam can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of re-stress on tested devices. By combining the characterized L_dam and N_it quantitatively, the results show that the damage at L_dam and V_GS≈V _DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Structure-enhanced MOSFET degradation due to hot-electron injection

Device degradation due to channel hot-electron injection in several nonconventional MOSFET structures including minimum-overlap gate, offset gate, graded drain, and lightly doped drain (LDD) structures are evaluated. In these nonconventional structures the device degradation is much faster than that in conventional devices when biased with the same amount of hot electrons in the channel. This faster degradation rate is proposed to be due to external channel pinchoff at the more lightly doped drain edge. This behavior implies even more severe constraints on the operating regime for these nonconventional device structures at submicrometer gatelengths to maintain adequate reliability margins.     

Examination of oxide damage during high-current stress of n-MOStransistors

Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I _d-V_gs characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO₂ interface. It is shown that damage from low drain current stress occurs at the Si-SiO₂ interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO₂ interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO₂ interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO₂ interface at the drain junction edge     

Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs

High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.