5G 毫米波三频单阶 ISGW 腔体滤波器设计

本文提出了一种紧凑的三频单阶集成基片间隙波导( ISGW)腔体滤波器。 为了限定腔内模式数量,通过分析ISGW 腔模的谐振频率关系,设计了一个腔内只有三个谐振模式的 ISGW 腔体。 为了改善频段之间的带外抑制同时提高频率选择性,提出了新颖的三频单阶滤波响应耦合拓扑,然后在研究该腔体内的腔模位于四个端口处的耦合关系的基础上,设计了不同于传统输入输出端口的位置关系,其输入输出端口各有一个“U”型槽,呈 90°布局作馈电结构。 最后得到了三个通带内只有一个谐振模式的三频单阶腔体滤波器。 对该滤波器进行了建模、仿真和构造,然后利用网络分析仪测量了其端口反射传输系数。 测试结果表明,该滤波器的三个频段的中心频率分别为 f01 = 24. 25 GHz、f02 = 27. 57 GHz 和f03 = 31. 14 GHz;插入损耗(IL)分别为IL1 =1. 58 dB、IL2 = 1. 07 dB和IL3 =2. 51 dB;有限传输零点(FTZ)分别为FTZ1 =20. 55 GHz、FTZ2 = 26. 20 GHz、FTZ3 = 29. 37 GHz 和 FTZ4 = 33. 17 GHz;频段之间的带外抑制优于 13 dB。 测量结果与仿真结果之间存在一定的频移,但相对带宽优于仿真结果。 相比较传统滤波器器件,该款滤波器具有设计频段高、在毫米波频段带外抑制水平高、频率选择性强、整体体积小和质量轻等优势。     

一种基于HTCC的高隔离度开关电路设计

基于开关芯片实现的开关电路是射频前端的基本单元之一,其功能是实现射频信号的导通和关断,在小功率射频信号传输中应用广泛。本文以6 GHz～15 GHz超宽带、60 dB隔离度为设计目标,采用高温共烧陶瓷基板工艺和级联腔体隔离技术,以级联开关芯片为基本电路结构,设计了高隔离度开关电路。该电路包含一只限幅器和两只吸收式砷化镓单刀单掷开关,装配于两个相邻的隔离腔体结构中,通过类同轴垂直传输过渡到基板内对称带状线传输结构,再辅以两侧地孔,实现电磁屏蔽。对开关电路进行电磁场建模仿真,结果表明该结构具有良好的传输特性和隔离特性;在射频前端电路制造完成后对开关电路进行装配和测试,测试结果与建模仿真结果一致性高,验证了本文设计的开关电路具有高隔离度特性。     

基于叠层SIW滤波器的高集成硅基毫米波收发前端

提出了一种基于硅基晶圆级封装技术的小型化Ka频段收发前端,实现了接收通道、发射通道与本振产生电路的一体集成。该收发前端采用嵌入叠层型基片集成波导(SIW)滤波器结构实现高选择性预选滤波与低损耗垂直互连过渡的一体化设计。测试结果表明,该Ka频段滤波器中心损耗1 dB,1 dB带宽4.02 GHz,中心频偏5 GHz处抑制度优于35 dB,仿真与测试结果吻合良好。在前端模组设计中,通过采用硅基微腔屏蔽实现紧凑尺寸下各功能单元的隔离,通过采用1/4波长短路传输线结构抑制电源、控制等低频信号对接收中频的干扰,最终实现了该毫米波收发前端的小型化集成,其尺寸仅为20 mm×20 mm×1.25 mm,主要电性能满足设计要求。     

基于半模基片集成波导的双频段缝隙天线

基于半模基片集成波导技术,提出了一种适用于微波集成电路的双频段缝隙天线。该双频段天线由馈电微带线,一段半共面波导结构和具有辐射缝隙的半模基片集成波导谐振腔构成,利用半模基片集成波导谐振腔的多模式工作特性实现了天线多频段特性。仿真和测试结果表明,该天线能同时工作在C频段(谐振频率5.74 GHz,S11=-21.86 dB)和X频段(谐振频率11.33 GHz,S11=-25.09 dB),不需要同时采用两个天线,具有便于和平面电路集成、体积小、结构简单、成本低等优点。     

毫米波双通带基片集成波导滤波器设计

提出了一种新型毫米波双通带基片集成波导(SIW)滤波器,该滤波器由双模基片集成波导和双模带线谐振器构成。其中双模带线谐振器嵌入到双模基片集成波导谐振腔中,不占据额外的电路面积,利用双模带线谐振器的TEM模和双模基片集成波导谐振腔的两个简并模式TE102、TE201,可分别形成两个相互独立的通带,因此该滤波器的设计具有很大的灵活性。所设计的双通带滤波器具有三个传输零点,实现了良好的带外抑制和带间隔离度。该双通带滤波器工作于28.4GHz和32.2GHz,3dB带宽分别为2%和3%。最终的测试结果和仿真结果相吻合,证明了该设计方法的可靠性。     

基于慢波特性扇形SIW的可调带通滤波器

提出了一种具有慢波特性的扇形基片集成波导谐振腔,设计了一款小型化双频带通滤波器,相较于传统SIW带通滤波器,该滤波器小型化率为64%。通过引入金属盲孔结构实现了滤波器双频带中心频率的调节,同时,采用源负载耦合结构,在带外产生了4个传输零点,实现了滤波器的高选择特性。测试结果表明,滤波器的双通带中心频率分别为4.86 GHz和6.81 GHz,3 dB带宽分别为238 MHz和212 MHz,双频带插入损耗分别优于0.9 dB和1.1 dB,与仿真结果基本一致。     

X波段Si基片集成脊波导MEMS环行器

基于波导传输理论设计并制备了一款Si基片集成脊波导(RSIW)微电子机械系统(MEMS)环行器,该环形器以高阻硅作为衬底材料,采用高精度三维MEMS加工工艺制备而成。通过在基片集成波导(SIW)结构中添加脊梁结构,形成RSIW传输结构,使传输主模TE10模的截止频率比矩形波导TE10模的低,从而实现相同频率下更小的器件尺寸。同时,通过电磁仿真软件对射频匹配和磁场分布进行了精确的建模仿真,完成了Si基片集成脊波导MEMS环行器的仿真设计。制备了尺寸为6 mm×6 mm的环行器样品并进行了测试,结果验证了仿真设计的准确性,其工作频率为8～12 GHz,回波损耗大于20 dB,隔离度大于18 dB,插入损耗小于0.5 dB。实现优良微波特性的同时,相比于常规的SIW结构环行器尺寸缩小了20%左右。     

半模SAFSIW谐振腔耦合带通滤波器设计与实现

空气隙填充基片集成波导(Slab Air-Filled Substrate Integrated Waveguide,SAFSIW)作为一种新型的导波结构,被广泛应用于毫米波传输线以及无源电路的设计,由于SAFSIW 中空气隙的存在,其相较于传统的SIW 具有更高Q值。本文基于半模双腔耦合SAFSIW 设计并实现了一款中心频率为19 GHz 的带通滤波器。为了改善滤波器的带外抑制,通过给谐振器并联枝节线结构,在滤波器的上边28 GHz 处,引入一个传输零点,大大改善了滤波器的带外抑制特性。利用双面覆铜的LCP 基板进行了滤波器的加工,并对其进行测试。测试结果表明,该滤波器中心频率为19 GHz,相对带宽达18%,插入损耗优于-4.2 dB,回波损耗小于-16 dB。由于上边带传输零点的引入,该滤波器在28.5 GHz 时,上边带抑制达到-36 dB 以下。实物测试相比于仿真结果有一定的恶化,主要原因是由于SMA转接头带来的损耗以及HMSAFSIW谐振腔的加工误差所导致。     

具有小中心频率比的紧凑型双频带滤波器

采用平面双模谐振器设计了一款新颖的具有小中心频率比的紧凑型双频带滤波器。该滤波器的两个工作频段的中心频率分别为5G WiFi的两个有用频段5.2 GHz和5.8 GHz,中心频率比为1:1.1。实现了具有四个传输零点的双通带响应,其中位于两个频带中间的两个传输零点由谐振器自身产生,很好地抑制了通带间的无用频段。另外两个传输零点由源负载耦合结构产生。加工并测试了该滤波器,两个通带的3 dB相对带宽为5.8%和5.2%,通带内的插入损耗小于0.8 dB,四个传输零点分别位4.52, 5.50,5.50和6.50 GHz,实验和仿真结果吻合,验证了结构的有效性。     

多层LCP基板中宽带槽线耦合结构的设计与实现

槽线耦合结构作为多层电路结构中的核心单元,其特性直接决定整个系统性能的优劣。基于三层LCP基板设计了一款Ka波段宽带微带线-槽线-微带线垂直耦合结构,通过接地层的槽线结构实现了异面微带线间信号传输。仿真结果显示,在23～43.62 GHz的通带内,该结构的插入损耗约为-1 dB,回波损耗优于-16 dB。为进一步改善槽线耦合结构的传输特性,创新性地在四层LCP基板底层加载3 mm×1 mm的开路枝节线,在24.45～41.93 GHz频段内插入损耗约为-0.95 dB,回波损耗优于-21 dB。基于LCP多层板技术,制备了槽线耦合结构,测试结果显示,该结构在23.16～40.35 GHz频率范围之内,插入损耗约为-2 dB,回波损耗优于-14 dB。该研究将为多层LCP基板在微波毫米波射频系统集成方面的应用提供实验依据。     

0.18 μm 21-27 GHz CMOS UWB LNA with 9.3 ± 1.3 dB gain and 103.9 ± 8.1 ps group delay

A 21-27 GHz CMOS ultra-wideband low-noise amplifier (UWB LNA) with state-of-the-art phase linearity property (group delay variation is only ± 8.1 ps across the whole band) is reported for the first time. To achieve high and flat gain (S₂₁) and small group delay variation at the same time, the inductive series peaking technique was adopted in the output of each stage for bandwidth enhancement. The LNA dissipated 27 mW power and achieved input return loss (S₁₁) of 213 to 220.1 dB, output return loss (S₂₂) of 28.2 to 230.2 dB, flat S21 of 9.3 ± 1.3 dB, reverse isolation (S₁₂) of 252.7 to 273.3 dB, and noise figure of 4.9?6.1 dB over the 21-27 GHz band of interest. The measured 1 dB compression point (P_1dB) and input third-order intermodulation point (IIP3) were 214 and 24 dBm, respectively, at 24 GHz.     

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P⁺ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S₂₁| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.     

3–10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt–Shunt Feedback Technique

In this paper, we demonstrate an SiGe HBT ultra-wideband (UWB) low-noise amplifier (LNA), achieved by a newly proposed methodology, which takes advantage of the Miller effect for UWB input impedance matching and the inductive shunt-shunt feedback technique for bandwidth extension by pole-zero cancellation. The SiGe UWB LNA dissipates 25.8-mW power and achieves S₁₁ below -10 dB for frequencies from 3 to 14 GHz (except for a small range from 10 to 11 GHz, which is below -9 dB), flat S₂₁ of 24.6 plusmn 1.5 dB for frequencies from 3 to 11.6 GHz, noise figure of 2.5 and 5.8 dB at 3 and 10 GHz, respectively, and good phase linearity property (group-delay variation is only plusmn28 ps across the entire band). The measured 1-dB compression point (P₁ dB) and input third-order intermodulation point are -25.5 and -17 dBm, respectively, at 5.4 GHz.     

First demonstration of monolithic InP-based HBT amplifier with PNPactive load

An InP-based integrated HBT amplifier with PNP active load was demonstrated for the first time using complementary HBT technology (CRBT). Selective molecular beam epitaxy (MBE) regrowth was employed and a merged processing technology was developed for the monolithic integration of InP-based NPN and PNP HBTs on the same chip. The availability of PNP devices allowed design of high gain amplifiers with low power supply voltage. The measured amplifier with PNP HBT active load achieved a voltage gain of 100 with a power supply (V_CC) of 1.5 V. The corresponding voltage swing was 0.9 V to 0.2 V. The amplifier also demonstrated S₂₁ of 7.8 dB with an associated S₁₁ and S₂₂ of -9.5 dB and -8.1 dB, respectively, at 10 GHz     

Integrated metal magnetic film coupled line circulators for monolithic microwaveintegrated circuits

A new structure of integrated planar metal magnetic film coupled line (MMFCL) circulators is presented, in which a metal magnetic film is used instead of ferrite materials. Simulation was performed with HFSS based on coupled-mode theory. An insertion loss of 4 dB and isolation of -13.5 dB between S₂₁ and S₁₂ over a frequency band of 3 GHz (from 36.5 to 39.5 GHz) were realised for a three-port MMFCL circulator     

一种小型化超宽带MIMO天线设计

提出了一种基于槽天线的小型化、高隔离度的超宽带(Ultra Wideband, UWB)多入多出(Multiple-Input Multiple-Output, MIMO)天线.该MIMO天线由两个槽天线单元构成, 为了增加天线阻抗带宽, 每个槽天线单元由末端带有圆形贴片的微带线和末端为圆形的槽线两部分耦合馈电.采用在地板上开槽和方向图分集方法, 减少地板表面波和空中电磁波影响, 达到提高天线隔离度的目的.数值仿真和实验结果表明:该天线在3.1~11 GHz频段内满足端口反射系数|S₁₁| < -10 dB, 隔离度|S₁₂|在7~11 GHz频段内小于-25 dB, 在3.1~7 GHz频段内小于-16 dB, 并根据仿真和测试S参数计算了包络相关系数.     

A Ka-Band CMOS Wilkinson Power Divider Using Synthetic Quasi-TEM Transmission Lines

This work presents a Ka-band two-way 3 dB Wilkinson power divider using synthetic quasi-transverse electromagnetic (TEM) transmission lines (TLs). The synthetic quasi-TEM TL, also called complementary-conducting-strip TL (CCS TL), is theoretically analyzed. The equivalent TL model, whose production is based on the extracted results, is applied to the power divider design. The prototype is fabricated by the standard 0.18 mum 1P6M CMOS technology, showing the circuit size of 210.0 mumtimes390.0 mum without contact pads. The measurement results, which match the 50 Omega system, reveal perfect agreements with those of the simulations. The comparison reveals the following characteristics. The divider exhibits an equal power-split with the insertion losses (S₂₁ and S₃₁) of 3.65 dB. The return losses (S₁₁, S₂₂ and S₃₃) of the prototype are higher than 10.0 dB from 30.0 to 40.0 GHz.     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

Fabrication and Characteristics of 40-Gb/s Traveling-Wave Electroabsorption Modulator-Integrated DFB Laser Modules

We have developed 40-Gb/s traveling-wave electroabsorption-modulator-integrated distributed feedback laser (TW-EML) modules using several advanced technologies. First, we have adopted a selective area growth (SAG) method in the fabrication of the 40-Gb/s EML device to provide active layers for the laser and the electroabsorption modulators (EAMs) simultaneously. The fabricated device shows that the measured 3-dB bandwidth of electrical-to-optical (E/O) response reaches about 45 GHz and the return loss (S₁₁) is kept below -10 dB up to 50 GHz. For the module design of the device, we mainly considered electrical and optical factors. The measured S₁₁ of the fabricated 40 Gb/s TW-EML module is below -10 dB up to about 30 GHz and the 3-dB bandwidth of the E/O response reaches over 35 GHz. We also have developed two types of coplanar waveguide (CPW) for the application of the driver amplifier integrated 40 Gb/s TW-EML module, which is a system-on-package (SoP) composed of an EML device and a driver amplifier device in a module. The measured S₁₁ of the two-step-bent CPW is below -10 dB up to 35 GHz and the measured S₁₁ of the parallel type CPW is below -10 dB up to 39 GHz.     

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range