64 bit monolithic floating point processors

Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems.     

A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions

An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.<>     

A monolithic 14 bit A/D converter

A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped operational amplifier followed by a strobed flip-flop to freeze the output data. In the digital part, current mode logic (CML) is used for speed and low interference generation with respect to the analog circuitry. Digital input and outputs are TTL compatible. A low-noise, high-stability reference source with a temperature dependence of /spl plusmn/0.5 ppm//spl deg/C over -20 to +85/spl deg/C completes the A/D function. The chip is processed in a standard bipolar process using double layer interconnection. The die size is 3.5/spl times/4.4 mm/SUP 2/.     

A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.<>     

实现64位计算的OpteronTM处理器

AMD 推出与业内标准 x86 结构兼容的64位处理器AMDOpteron,这是目前最高性能的2路和4路服务器处理器。在美国纽约市举行 AMD Opteron处理器产品发布会上,IBM宣布将推出一款基于 AMD Opteron 处理器的针对高性能计算的服务器产品。同时,微软也承诺将为这款处理器开发一套 64 位操作系统,测试版 (beta version) 定于2003 年年中推出。专为服务器及工作站设计的 AMDOpteron 处理器首次将x86指令体系(ISA)扩展到 64 位,也是被称为AMD64的新一代计算标准下的新一款处理器。AMD64 是遵循业内标准 x86 ISA 结构的进化路径自然发展而…     

A compact, monolithic microwave demodulator-modulator for 64-QAMdigital radio links

The design, fabrication and performance of a monolithic microwave direct modulation modulator-demodulator are presented. The subsystem is designed to work in a 64-QAM digital radio link. At this level of modulation, it is necessary to have some possibilities of phase and amplitude trimming by external voltages to achieve sufficient accuracy. The circuit includes elementary functions such as quadrature and in-phase splitters, and circuits giving the possibility to adjust phases and amplitudes for 64 QAM and higher level modulation. The design is such that the same chip can be used either as a direct demodulator or as a modulator. This complex circuit of small dimensions (2.7 mm×3.65 mm) exhibits good demodulation and modulation performances. The overall performances of this monolithic circuit are achieved without degrading the DC yield     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

一种新型硬件可配置公钥制密码协处理器的VLSI实现

提出了一种新型的硬件可配置的密码协处理器，同时适用于GF(p)和GF(2^m)两种域，可以实现RSA和ECC两种目前主流的加密算法。同时又具备硬件可配置的特点，可以完成32—512bit的模乘运算而无需对硬件做任何修改。本文的密码协处理芯片用TSMC0．35μm标准单元库综合，可以工作在100MHz时钟下，等效单元45k等效门，512bit的模乘运算速度可以达到190kbit／s，一次椭圆曲线上的233bit的点加运算只需18μs。     

A CMOS floating-point vector-arithmetic unit

This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 μm double-metal n-well CMOS technology and achieves a normalized peak performance of 220 MFLOPS     

A floating-point advanced cordic processor

In this paper, a novel architecture of a floating-point digital signal processor is presented. It introduces a single hardware structure with a full set of elementary arithmetic functions which includessin, cos, tan, arctanh, circular rotation andvectoring, sinh, cosh, tanh, arctanh, hyperbolic rotation andvectoring, square root, logarithm, exponential as well asaddition, multiplication anddivision. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) and the Convergence Computing Method (CCM) algorithms for computing arithmetic functions and it is fully parallel and pipelined. Its advanced functionality is achieved without significant increase in hardware, in comparison to ordinary CORDIC processor, and makes it an ideal processing element in high speed multiprocessor applications, e.g. real time Digital Signal Processing (DSP) and computer graphics.     

A monolithic 14 bit/20 /spl mu/s dual channel A/D converter

A 14-bit monolithic coarse-fine integration A/D converter with 20-/spl mu/s conversion time is described. The IC has internal sample-and-integrate circuits and dual-channel A/D conversion capability. Overall performance, including sample-and-integrate circuits, is 0.01% distortion and 84-dB S/N ratio. All of the analog/digital circuits for dual-channel A/D conversion are integrated on a single chip by using an advanced nitride self-aligned (advanced-NSA) process.     

A floating-point digital receiver for MRI

A magnetic resonance imaging (MRI) system requires the highest possible signal fidelity and stability for clinical applications. Quadrature analog receivers have problems with channel matching, dc offset and analog-to-digital linearity. Fixed-point digital receivers (DRs) reduce all of these problems. We have demonstrated that a floating-point DR using large (order 124 to 512) FIR low-pass filters also overcomes these problems, automatically provides long word length and has low latency between signals. A preloaded table of finite impuls response (FIR) filter coefficients provides fast switching between one of 129 different one-stage and two-stage multrate FIR low-pass filters with bandwidths between 4 KHz and 125 KHz. This design has been implemented on a dual channel circuit board for a commercial MRI system.     

A 600-MHz superscalar floating-point processor

The floating-point unit of a 600-MHz, out-of order, superscalar RISC Alpha microprocessor is described. The unit achieves 59 SpecFP95 and can transfer register data at up to 9.6 GB/s. It has two independent pipelines for multiply and add/subtract operations, with iterative divide and square-root circuits, and is fabricated in a 2.2-V, 0.35-μm CMOS process     

A bit is a bit is a bit?

Bits are among the most anonymous, most elusive entities in the universe. Bits weigh nothing, occupy no space, obey no physical law, can be created spontaneously from nothingness, and can be endlessly replicated. Each in itself is the merest quantum of the Information Age, yet taken together all those little 1s and 0s are acting as if they were the most important force on the planet. And if you want indestructibility, then a bit is forever. The author briefly discusses the role of the bit in today's society     

一种64位高速PCI总线接口的设计与实现

设计了一种基于PCI9656的高速PCI总线接口,数据传输主要为DMA方式。文中介绍了PCI9656的内部结构和功能,讨论了其WDM驱动开发过程,分析了其局部总线在进行DMA传输时的配置时序,提出了一些设计中需要注意的问题。实际应用结果表明,该总线接口性能稳定且优良,可以应用于高速数据传输系统。     

BC7280/818位/16位LED数码管显示及64键键盘控制芯片的特点和应用

BC7280/81是比高公司推出的8位/16位LED数码管显示及键盘接口专用控制芯片，可用于控制16位数码管或128只独立的LED。文中介绍了BC7280/81的主要特点，引脚功能，主要参数及接口时序，给出了它的典型应用电路和汇编语言程序。     

Garbage collection coprocessor system

The intelligent cell memory system is a coprocessor system to achieve on-the-fly garbage collection. Analyses on its experimental results reveal its advantages over conventional garbage collection approaches     

A programmable floating-point cell for systolic signal processing

The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.     

A 20 b dynamic-range floating-point data acquisition system

The design and engineering of a floating-point data-acquisition system are described. The system has both automatic gain and software-programmable gain adjustment features. In automatic gain adjustment mode, the gain is set automatically dependent on the input amplitude so that the full conversion resolution is maintained irrespective of the signal dynamic range. A high-speed flash ADC with an approximately 35 ns conversion time is used to convert the signal quickly into 8 b data. A programmable array logic (PAL) then transfers this 8 b digital data into 12 b information for setting the gain of the variable-gain amplifier. The amplifier gain settings are all powers of two; thus, the normalization of the digitized data requires only a bit shifting operation and no complex software division. The gain information and the 12 b sampling ADC output increase the dynamic range to 20 b. The software package includes commands needed for the system initiation, automatic gain or software programmable gain selection, sampling and conversion, and data normalization