Impact of Ge implantation on the electrical characteristics of TiSi2 p+/n shallow junctions with an a-Si (or apoly-Si) buffer layer

A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi₂ film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi₂ contacted p⁺/n junctions was examined. After subsequent implantation of Ge⁺ and B⁺ into the TiSi₂ film, samples were annealed at different temperatures to form p ⁺/n junctions and C54-TiSi₂. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi₂/Si interfaces were even smooth. Therefore, p⁺/n junctions with a very low leakage current (0.192 nA/cm ² at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400     

Self-aligned silicided (PtSi and CoSi2) ultra-shallow p+/n junctions

Ultra-shallow p+/n junctions (<100 nm) demonstrating excellent I-V characteristics have been fabricated with self-aligned PtSi. Junctions were formed by rapid thermal annealing (RTA) 〈100〉 Si preamorphized with Sn+ and implanted with BF2+. Subsequently, low-temperature RTA in N2of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm^-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi2overlayer.     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Simultaneous formation of silicide ohmic contacts and shallow p+-n junctions by ion-beam mixing and rapid thermal annealing

Low-resistivity, uniform molybdenum silicide layers, and shallow p⁺-n junctions with good electrical characteristics have been formed using ion-beam mixing and rapid thermal annealing (RTA). Detailed reverse leakage current data on RTA annealed diodes, which were formed by implanting BF2⁺into Si substrates through the molybdenum films deposited on Si, are presented. The process has a great potential for CMOS fabrication with self-aligned silicided source, drain, and gate.     

Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Various effects of silicidation on shallow p+ junctionsformed by BF2+ implantation into thin poly-Sifilms on Si substrates

Various effects of silicidation on shallow p⁺ n junctions formed by the scheme that implants BF₂⁺ ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones     

Evaluation of the profile constants of p+-n-n+hyperabrupt junctions

A method for evaluating the profile constants of a p⁺-n-n⁺hyperabrupt junction is given. The method is useful in the design and characterization of hyperabrupt tuning varactors.     

Abnormal junction profile of silicided p+/n shallowjunctions: a leakage mechanism

The leakage mechanism in p⁺/n shallow junctions fabricated using Co silicidation and shallow trench isolation processes has been investigated using transmission electron microscopy (TEM) combined with selective chemical etching. TEM and TSUPREM-4 simulation results show that dopant profiles bend upward near the edge of the active region. The formation of the abnormal profile is attributed to transient enhanced diffusion induced by source/drain implantation. Based on the TEM and simulation results, it is suggested that the shallower junctions formed near the active edge can serve as a source for leakage current in the silicided p+ /n shallow junctions     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

6H-SiC p+-n junctions fabricated by berylliumimplantation

The use of beryllium (Be) as an alternate p-type dopant for implanted silicon carbide (SiC) p⁺-n junctions is experimentally demonstrated. The implanted layers have been characterized with photoluminescence (PL) as well as secondary ion mass spectrometry (SIMS) measurements. In comparison with boron implanted p ⁺-n junctions, Be-implanted junctions show improvement in the forward characteristics while exhibiting slightly higher reverse leakages. The activation energies extracted from the forward conduction and reverse leakage characteristics of the Be-diodes are 1.5 eV, and 0.13 eV, respectively. Moreover, activation energy extraction in the forward ohmic region reveals the Be impurity level at 0.38±0.04 eV. The minority carrier lifetime extracted from reverse recovery measurements is as high as 160 ns for the Be-diodes compared to 82 ns obtained for the B-diodes     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

Double-drift-region (p+pnn+) avalanche diode oscillators

The advantages of a double-drift-region avalanche diode oscillator are discussed. Conventional structures (p⁺nn⁺or n⁺pp⁺) are essentially single-drift-region devices in that transit-time delay (for IMPATT mode) and zone transit (for TRAPATT mode) occur in a single region of one impurity type. The proposed structure (p⁺pnn⁺) has two drift regions and is essentially two complementary avalanche diode oscillators in series.     

Device simulation of submicrometer gate p+-i-p+ diamond transistors

Two-dimensional device simulation of submicrometer gate diamond p ⁺-i-p⁺ transistors with a SiO₂ gate insulator was investigated using the MEDICI device simulation program. A large modulation of the source-to-drain current was obtained in the accumulation mode. The computed diamond device characteristics were equivalent or better than the simulation results of 6H-SiC MESFET's. It was concluded that the problems in diamond MESFET associated with the deep acceptor levels due to boron doping can be overcome in the p⁺ -i-p⁺ diamond FET's because of the hole injection and the space charge limited current     

Low avalanche noise characteristics in thin InP p+-i-n+ diodes with electron initiated multiplication

We have performed electron initiated avalanche noise measurements on a range of homojunction InP p⁺-i-n⁺ diodes with “i” region widths, w ranging from 2.40 to 0.24 μm. In contrast to McIntyre's noise model a significant reduction in the excess noise factor is observed with decreasing w at a constant multiplication in spite of α, the electron ionization coefficient being less than β, the hole ionization coefficient. In the w=0.24 μm structure an effective β/α ratio of approximately 0.4 is deduced from the excess noise factor even when electrons initiate multiplication, suggesting that hole initiated multiplication is not always necessary for the lowest avalanche noise in InP-based avalanche photodiodes     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

Forward transient characteristics of gold-doped silicon p+-n-n+diodes

The transient response of high-resistivity long-base low-lifetime p⁺-n-n⁺silicon diodes was examined experimentally. The diodes were doped with gold in order to reduce the minority carrier lifetime. Voltage oscillations were observed at different current levels. A large inductive effect was shown to exist when the diode was forward biased in a negative resistance region of the dc voltage-current characteristics.