采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

开关信号理论与绝热CMOS电路设计

重新定义了钟控信号的表示方法,发展了适用于绝热电路的开关级设计理论.设计了实现全部钟控信号的基本单元电路,这些电路包括单轨和双轨结构,并给出了它们的多种级联方式.所提出电路的功耗与其他绝热电路相当,并工作于二相正弦功率时钟,因此可降低时钟电路的设计难度.这些电路可分别应用于需要基0信号和基1信号的绝热电路设计中.与以往大部分绝热电路不同的是,应用所提出的电路结构可以实现在同一时钟相位有多级电路同时参加运算.这一特性可以有效减少实现复杂逻辑电路时的等待时间以及实现流水结构时所需插入的缓冲器数目.通过对基0信号2∶1数据选择器和基1信号全加器的设计及SPICE模拟,验证了所提出设计技术的有效性以及电路的低功耗特性.     

具有反馈结构的PAL-2NF电路

在分析PAL - 2 N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL - 2 NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL - 2 NF电路的设计方法,并在不同时钟频率下用1 .2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL - 2 NF反相器/缓冲器电路在功率时钟频率1 0 MHz时都比相应的PAL - 2 N电路节省93%以上的功耗,在4 0 0 MHz时功耗节省也可达4 0 % .由于几乎完全消除了输出端的悬空现象和逻辑0的“第三态”现象,PAL - 2 NF电路可以工作于更高的时钟频率和更低的输出波形畸变     

具有反馈结构的PAL-2NF电路

在分析PAL-2N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL-2NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL-2NF电路的设计方法,并在不同时钟频率下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL-2NF反相器/缓冲器电路在功率时钟频率10MHz时都比相应的PAL-2N电路节省93%以上的功耗,在400MHz时功耗节省也可达40%.由于几乎完全消除了输出端的悬空现象和逻辑0的"第三态"现象,PAL-2NF电路可以工作于更高的时钟频率和更低的输出波形畸变.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficient PAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficientPAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变     

一种改进的能量回收逻辑电路

文本分析了能量回收电路的功耗组成，指出非绝热损失是能量回收电路的主要功耗能量来源，提出了一种改进的能量回收逻辑电路IERL。IERL电路增加了额外的回收路径，能够显著降低电路的非绝热损失，HSPICE模拟结果表明，IERL电路具有很好的低功耗性能。同时，给出了IERL电路的复杂逻辑门设计与级联方式，用0．8μm DPDM工艺实现了2位IERL全加器电路和两相正弦功率时钟电路。     

一种交叉耦合低功耗传输门绝热逻辑电路

提出了一种新的能量恢复型电路—— Transmission Gate Adiabatic Logic(TGAL)。该电路由交叉耦合的 CMOS传输门完成逻辑运算与能量恢复 ,对负载的驱动为全绝热过程。TGAL电路输出端始终处于箝位状态 ,在整个输出期不存在悬空现象并具有良好的信号传输效果。分析了 TGAL反相器的能耗 ,并与静态 CMOS电路及部分文献中绝热电路进行了比较。使用 TGAL构成门电路与时序系统的实例被演示。应用 MOSIS的0 .2 5 μm CMOS工艺参数的模拟结果表明 ,与传统 CMOS和 2 N-2 N2 P绝热电路相比 ,TGAL电路在 1 0 0 MHz工作频率时分别节省 80 %与 60 %以上的功耗。     

45mm低功耗、高性能Zipper CMOS多米诺全加器设计

提出了电荷自补偿技术,此技术利用P型多米诺电路动态结点的放电对N型多米诺电路的动态结点充电,并在此技术基础上综合应用双阈值技术和多电源电压技术,设计了新型低功耗、高性能Zipper C?dOS多米诺全加器.仿真过程中提出了功耗分布法,精确找到了电荷自补偿技术的最优路径.仿真结果表明,在相同的时间延迟下,与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比,新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7%,静态功耗分别减小了41%,20%和43%.最后,分析并得到了新型全加器漏电流最低的输入矢量和时钟状态.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

Scaling trends in energy recovery logic: an analytical approach

This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

一种新的低功耗CMOS三值电路设计

提出一种新的静态电压型CMOS三值电路设计方案.该方案具有电路结构规则,输入信号负载对称等特点,是一种具有互补输入-输出的双轨三值逻辑电路.由于电路中同时采用pMOS和nMOS两种传输管,从而保证了输出信号具有完整的逻辑摆幅和高噪声容限.尤为重要的是该设计方案是基于标准CMOS工艺而无需修改阈值电压,且结构较简单.采用0.25μm CMOS工艺参数及3V电源的计算机模拟结果同时表明所提出的电路设计具有高速及低功耗的特点.     

一种软件级双轨逻辑的完整实现方案

旁路攻击是一种通过分析密码设备在运行时所产生的旁路信息来分析该密码设备的秘密信息的方法.Paul Kocher等人在1998年提出的功耗分析现在已经是针对密码设备的旁路攻击中非常常见的一种.在硬件实现的密码设备中,双轨逻辑是一种有效的抵抗功耗分析的方法,它通过用两位物理比特来表示一位逻辑比特,使数据0和1的表述对称,从而平衡了功耗的大小.对于软件实现的密码设备,也可以借鉴双轨逻辑的思路,这里给出了一个较为完备的软件级双轨逻辑方案,解决了一些前人方案的不周全指出,并之后在一个DES算法的实验中,验证方案的有效性.     

Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder.     

A 90nm Passive RFID Tag's Custom Baseband Processor for Subthreshold Operation Below 0.3V

In the design of passive Radio frequency (RF) tags' baseband processor, subthreshold timing and wide-range-Process, voltage and temperature (PVT) varia-tion problems are the bottlenecks to extend the tag's work-ing range. A sophisticated processor is presented based on the EPC and ISO protocol. Power-aware ideas are applied to the entire processor, including data link portions. In-novatively, a novel custom ratioed logic style is adopted in critical logic paths to fundamentally speed up the cir-cuit operations at ultra-low-voltage. The proposed base-band processor was fabricated in 90nm CMOS, another baseband processor design by regular standard-cell-based design flow was also fabricated for comparison. In mea-surement the proposed design indicates good robustness in wide-range supply and frequency variation and much more competent for subthreshold operation. It can oper-ate at minimum 0.28V supply with power consumption of 129nW.     

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.     

Low depth, low power carry lookahead adders using threshold logic

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

大功率脉冲测量雷达应对电压跌落方法研究

针对交流电源短暂电压跌落引起市电直供的大功率脉冲测量雷达伺服、发射机和水冷系统保护停机的问题,叙述了雷达系统组成及对应功率容量。分析了采用双变换不间断电源和市电同时向伺服系统、发射机及水冷系统的低压控制电路和大功率部件区别供电的可行性。提出了改进分机低压控制线路和可编程逻辑控制器控保逻辑的建议,提高了雷达系统抵抗电压短暂跌落的能力。