CMOS单片光接收机的带宽设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的光电集成接收机.给出了DPD小信号电路模型和单片集成光接收机的带宽设计方法,给出限制DPD和光接收机带宽的重要因素,分析和模拟了这个光电集成接收机的带宽,用低成本的0.6μm CMOS工艺设计出1.71GHz带宽和49dB跨阻增益的接收机,并给出测试结果.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

New synthetic-heterodyne demodulator for an optical fiberinterferometer

A new algorithm for modulating a PZT stack using a sinewave signal instead of a saw-tooth signal was developed in order to resolve the flyback problem in a PZT driver. An improved synthetic heterodyne demodulator circuit was designed and arranged to interrogate the output signal from an interferometric sensor with a sinewave modulation (phase-generated carrier). The depth of modulation, or a gain amplifier in the circuit design, was adjusted such that the standard heterodyne signal could be formed. The result is a conventional PM-modulated carrier that can be demodulated using standard techniques, followed by a lock-in amplifier or a phase meter, to recover the phase shift in the sensing information. Implementing it into a path-matching differential interferometer for the signal modulation validates this new method. As compared to the conventional technique, modulating the PZT stack in a saw-tooth signal, this technique supplies a wider modulated frequency and, therefore, a wider frequency response in a sensing system. Finally, the new synthetic heterodyne is applied to a differential optical fiber refractometer for measuring the refractive index change. A lock-in amplifier is chosen as the demodulator to extract the phase shift. Therefore, the resolution of this sensing system is 7.52×10^-7 refractive index unit for a 120-μm length of the sensing cavity     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

Demonstration of CSRZ Signal Generator Using Single‐Stage Mach‐Zehnder Modulator and Wideband CMOS Signal Mixer

In this paper, we demonstrate an electrically band‐limited carrier‐suppressed return‐to‐zero (EB‐CSRZ) signal generator operating up to a 10 Gbps data rate comprising a single‐stage Mach‐Zehnder modulator and a wideband signal mixer. The wideband signal mixer comprises inverter stages, a mixing stage, and a gain amplifier. It is implemented by using a 0.13 μm CMOS technology. Its transmission response shows a frequency range from DC to 6.4 GHz, and the isolation response between data and clock signals is about 21 dB at 6.4 GHz. Experimental results show optical spectral narrowing due to incorporating an electrical band‐limiting filter and some waveform distortion due to bandwidth limitation by the filter. At 10 Gbps transmission, the chromatic dispersion tolerance of the EB‐CSRZ signal is better than that of NRZ‐modulated signal in single‐mode fiber.     

A Differential CMOS Current-Mode Variable Gain Amplifier with Digital dB-Linear Gain Control

A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.     

An area-efficient maximum-ratio-combining diversity receiver in 90 nm CMOS for free-space optical links

This paper presents a low-power imaging diversity front-end receiver employing the maximum-ratio-combining algorithm for free-space optical communication. It consists of seven signal channels and an output stage, each channel has a front-end transimpedance amplifier, a signal-to-noise ratio (SNR) estimator and a variable gain amplifier (VGA). The imaging receiver circuit was implemented in a 90 nm CMOS process. The maximum-ratio weighting is achieved with the SNR estimator and variable gain amplifier (VGA), which provides the signal with a gain proportional to the signal amplitude. The maximum ratio combining feature was demonstrated with two channels driven by photodiode emulation circuits for electrical characterization. The power dissipation for the whole chip is 43 mW from a single 1.2 V supply.     

A 3 GHz transimpedance OEIC receiver for 1.3-1.55 μm fiber-opticsystems

A high-performance metal-semiconductor-metal high-electron-mobility transistor (MSM-HEMT) transimpedance photoreceiver fabricated using OMCVD-grown InAlAs/InGaAs heterostructures on an InP substrate is discussed. This is the first demonstration of a monolithically integrated receiver amplifier that incorporates a cascode amplifier stage and a Schottky diode level-shifting stage implemented on InP-based optoelectronic integrated circuit (OEIC) photoreceivers. The transimpedance amplifier has an open-loop gain of 5.7 and a bandwidth of 3.0 GHz, which represent the highest gain and the highest speed performance reported for 1.3-1.55-μm-wavelength OEIC receivers     

PDP驱动芯片用RSDS接口电路设计

介绍了一种基于RSDS(减小摆幅差分信号传输)信号传输标准的PDP驱动芯片用接口电路设计,它包括PMOSFET输入CMOS差分放大器和电压源偏置电路.文章重点讨论了PMOSFET输入CMOS差分放大器的差模工作原理及影响其差模增益的因素.Spectre仿真结果表明,本文设计的RSDS接受器电路在输入信号频率为200 MHz的情况下能正常工作,实现了由RSDS信号转换为LVCMOS信号的功能.目前该接口电路已经应用于一款PDP驱动芯片中,作为高速数据传输接口.     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

High-speed photoreceivers using solder bumps and microstrip linesformed on a silicon optical bench

High-speed photoreceiver modules using silicon optical benches are described. These modules employ solder bumps for chip assembly and microstrip lines for electrical signal transmission. The assembly and wiring technologies are the same as those used in the planar lightwave circuit platforms we developed. A photoreceiver module consisting of a waveguide photodiode showed a very wide bandwidth greater than 20 GHz, and together with a spotsize-converted semiconductor optical amplifier, operated as an optical preamplifier that showed good receiver sensitivity of -20.3 dBm at 10 Gb/s nonreturn-to-zero     

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

Monolithically integrated multichannel SiGe/Si p-i-n-HBTphotoreceiver arrays

A low-power, short-wavelength eight-channel monolithically integrated photoreceiver array, based on SiGe/Si heterojunction bipolar transistors, is demonstrated. The photoreceiver consists of a photodiode, three-stage transimpedance amplifier, and passive elements for feedback, biasing and impedance matching. The photodiode and transistors are grown by molecular beam epitaxy in a single step. The p-i-n photodiode exhibits a responsivity of 0.3A/W and a bandwidth of 0.8 GHz at λ=0.88 μm. The three-stage transimpedance amplifier demonstrates a transimpedance gain of 43 dBΩ and a -3 dB bandwidth of 5.5 GHz. A single channel monolithically integrated photoreceiver consumes a power of 6 mW and demonstrates an optical bandwidth of 0.8 GHz. Eight-channel photoreceiver arrays are designed for massively parallel applications where low power dissipation and low crosstalk are required. The array is on a 250-μm pitch and can be easily scaled to much higher density. Large signal operation up to 1 Gb/s is achieved with crosstalk less than -26 dB. A scheme for time-to-space division multiplexing is proposed and demonstrated with the photoreceiver array     

CMOS fully differential second-generation current conveyor

The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 μm CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented     

Multiwavelength Frequency-Division-Multiplexed Light Source Based on Dispersion-Mode-Locking

Two dispersion-mode-locked laser experiments, each using a single, actively modulated linear optical amplifier and one or more fiber Bragg gratings, are presented. The first experiment demonstrates multiwavelength lasing based on dispersion-mode-locking. This mode-locking technique offers an intrinsic benefit that each wavelength is intensity modulated at a unique frequency, thus producing a frequency-division-multiplexed output. The second experiment shows fine-tuning of the dispersion-mode-locked lasing wavelength. Tunability from ~1546.5-1547 nm with a linewidth of ~0.06 nm was achieved. All experimental results should be applicable to other gain and dispersion media. A combination of the two experiments produces an excellent multiwavelength light source for sensing applications: for example, each of the multiple wavelengths can be tuned and locked to a gas absorption feature. The transmission at each wavelength can then be monitored using a single photoreceiver and a multichannel lock-in amplifier.     

4～8GHz GaAs HBT单片双平衡混频器

介绍了一种基于 GaAs HBT 的双平衡混频器.该混频器将射频、本振有源Balun集成其中,在RF和LO输入端分别采用不同的LC网络实现宽带的阻抗匹配.跨导级和开关单元之间采用交流耦合,并通过带宽扩展技术实现频带内的增益平坦.测量结果显示,该混频器匹配良好,射频端口S11在3～10 GHz频带内小于-10 dB.在固定中频200 MHz 情况下测试,在4～8 GHz射频频带内,平均增益10 dB,波动小于1 dB,中频输出端口对射频信号的隔离度优于25 dB,对本振信号的隔离度优于28 dB;本振-射频端口隔离度优于32 dB.在3.3 V直流电压下测得的功耗为66 mW.     

低噪声1.25Gb/s光接收机前端放大器

设计并实现了一种基于TSMC 0.25μm CMOS工艺的低噪声、1.25Gb/s和124dBΩ的光接收机前端放大器.跨阻放大器设计采用了有源电感并联峰化和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下,前端放大器工作速率达到了1.25Gb/s,在光功率为-17dBm的光信号输入下得到了清晰的眼图.芯片采用3.3V电压供电,功耗为122mW,差分输出电压幅度为660mV.     

A CMOS Ku-Band 4x Subharmonic Mixer

In this work, the design and measurement of a new 4x subharmonic mixer circuit is presented using CMOS 0.18 m technology. With an RF input signal at 12.1 GHz, and an LO signal at 3.0 GHz, an intermediate frequency of 100 MHz is produced (f_IF = f_RF - 4f_LO). The mixer uses a modified Gilbert-cell topology with octet-phase LO switching transistors to perform the quadruple subharmonic mixing. Included in the design is an active balun for the RF signal and a circuit that generates an octet-phase LO signals from a differential input. The mixer has a conversion gain of approximately 6 dB, 1-dB compression point of -12 dBm, IIP3 of -2 dBm, and IIP2 of 17 dBm. The circuit also exhibits excellent isolation between its ports (e.g. LO-RF: 71 dB, 4LO-RF: 59 dB).     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.