交流电波形对低压腐蚀铝箔微观形貌及性能的影响

对低压铝箔施加五种不同波形交流电,研究了不同交流电波形对低压铝箔腐蚀形貌及电性能的影响。结果表明:正弦波、三角波电流变化率较小,孔大而浅,不易产生并孔;而方波、梯形波电流均有一段平稳不变期,易产生并孔;变形正弦波一个周期存在四个峰值电流,发孔几率比正弦波要大,也易出现并孔。实验表明如果在不同腐蚀阶段选择适当的波形和频率,会使电子铝箔的性能指标有较大提高。     

Electron beam induced current investigations of active electrical defects in silicon due to reactive ion etching and reactive ion beam etching processes

Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results.     

Characterization of selective reactive ion etching effects on delta-doped GaAs/AlGaAs MODFET layers

The effects of selective reactive ion etching (SRIE) using SiCl₄/SiF₄ plasma on delta-doped GaAs/Al_0.3Ga_0.7As modulation-doped field-effect transistor (MODFET) structures and devices have been investigated. The results are compared with those of corresponding conventionally doped MODFETs. Hall measurements were conducted at 300 and 77 K to characterize the change in the transport properties of the two-dimensional electron gas due to low energy ion bombardment during the SRIE process. Delta-doped structures showed a smaller change in sheet carrier density and mobility compared to conventionally doped structures. Direct current and high frequency measurements were performed on the SRIE gate-recessed MODFETs. No significant change in threshold voltage was observed for the delta-doped MODFETs in contrast to an increase of about 300 mV for the conventionally doped MODFETs processed at a plasma self-bias voltage of −90 V and a 1200% overetch time. Maximum dc extrinsic transconductance and unity current gain cutoff frequency did not change with SRIE processing for either of the structures. This paper was presented at the Electronic Materials Conference at MIT, Cambridge, 1992.     

反应离子刻蚀InSb芯片引入的损伤研究

应用CH₄/H₂/Ar作为刻蚀气源对InSb微台面阵列进行了反应离子刻蚀,并对刻蚀后引入的损伤进行了分析。实验证实利用干法刻蚀与湿法腐蚀相结合的方法能有效地减少刻蚀引入的缺陷和损伤,获得较好的电学特性,达到低损伤刻蚀InSb材料的目的。     

电解电容器用铝箔腐蚀工艺研究

采用正交实验方法,选择腐蚀溶液的组成、腐蚀电压、腐蚀温度和时间四因素,探索影响环保型铝电解电容器用腐蚀箔性能的工艺参数。结果表明:当ψ(H2SO4∶HCl)为3∶1,电压为8V,温度为85℃,腐蚀时间85s时,可以获得高比容(0.59)高强度(弯折次数140)兼顾的性能。腐蚀溶液的组成、电压是影响腐蚀箔性能的主要因素。     

表面划痕对高纯铝腐蚀发孔的影响

采用沙砾平均粒径分别为10～14(#600)和5～7μm(#1000)砂纸打磨高纯单晶铝(100)和(124)面的方法,模拟生成轧辊划痕,用含有盐酸、硝酸和氢氟酸的混合溶液在表面进行发孔腐蚀,研究了表面位错露头发孔与划痕之间的关系。结果表明:试样表面点蚀坑由畸变能较高、表面张应力梯度较大的位错露头发孔腐蚀形成,表面划痕与位错应力场作用提高了腐蚀发孔率。#1000细砂纸比#600粗砂纸打磨试样可更多地提高表面腐蚀发孔率。(124)面腐蚀孔密度增幅小于(100)面。     

Reactive ion etching of dielectrics and silicon for photovoltaic applications

This paper investigates the reactive ion etching of SiO₂, Si₃N₄, and Si using CHF₃/O₂ plasma. In particular, we have characterized the time and rf power dependence of the carrier lifetimes in n‐ and p‐type FZ Si. The time dependence of reactive ion etching (RIE) at different rf powers provide insight into the two competing processes of damage accumulation and damage removal in the near‐surface region of the Si during plasma etching. The carrier lifetime, measured using the quasi‐steady‐state photoconductance (QSSPC) technique, has a quadratic dependence on the rf power, which can be related to changes in the dc self‐bias generated by the plasma at different rf powers. The change in carrier lifetime is similar in both n‐ and p‐type Si of the same doping concentration. Using this fact, together with the electronic properties of defects obtained by deep level transient spectroscopy (DLTS), we have modeled the injection‐dependence of the measured carrier lifetimes using the Shockley–Read–Hall model. The isochronal annealing behavior of plasma etched Si has also been studied. Copyright © 2006 John Wiley & Sons, Ltd.     

Surface contamination and damage from CF4 and SF6 reactive ion etching of silicon oxide on gallium arsenide

Two reactive ion etchants, CF₄ and SF₆, have been compared in terms of plasma characteristics, silicon oxide etch characteristics, extent of RIE damage, and formation of barrier layers on a GaAs surface after oxide etch. It was found that higher etch rates with lower plasma-induced dc bias can be achieved with SF₆ plasma relative to CF₄ plasma and that this correlates with higher atomic fluorine concentration in SF₆ plasma. RIE damage, measured by loss of sheet conductance in a thin highly-doped GaAs layer, could be modelled as a region of deep acceptors at a high concentration in the conductive layer. By relating the sheet conductance change to the modelled damaged layer thickness, it was found that the RIE-damaged thickness from both CF₄ and SF₆ plasmas had the same linear relation to plasma dc bias. Barriers to subsequent GaAs RIE were created during oxide overetch at the GaAs surface. The barriers were identified by XPS as ∼20 A of GaF₃ for CF₄ plasma and ∼30 A of GaF₃ on top of As_xS_y for SF₆ plasma. Ellipsometry was used to routinely determine the presence or absence of the barriers which could be removed in dilute ammonia.     

表观电化学参数对铝箔交流电侵蚀的影响

改变交流电密度 (J)、电解液温度 (T)及盐酸浓度 (ci)侵蚀电容器铝箔 ,并以表观电化学参数(J/ ci T)为依据 ,通过侵蚀铝箔的表面形貌和侵蚀箔比容的变化规律 ,研究了铝箔在纯盐酸中受〔Cl- 〕和〔H+ 〕影响的交流侵蚀机制。     

腐蚀频率对铝电解电容器用低压铝箔性能的影响

采用变频腐蚀工艺以及正交实验法,制备了铝电解电容器用低压铝箔,研究了腐蚀电源频率对所制低压铝箔腐蚀形貌及性能的影响。结果表明:腐蚀孔径随着电源频率的升高而变小,腐蚀电压随着频率升高而降低;频率25Hz为最佳工艺条件,所得腐蚀样品耐压值为83.2V,比容达16.07×10-6F/cm2。     

低压铝箔交流腐蚀工艺研究

考察了电解电容器用高纯铝箔在HCl-H2SO4-H3PO4混合酸体系中的交流腐蚀过程,综合配方和工艺两方面主要因素研究铝箔的交流扩面行为。结合SEM形貌分析,重点考察了前级电流密度、后级电流密度及腐蚀电量等对铝箔比容的影响,确定了最佳的低压铝箔交流腐蚀工艺,在2V化成,Cs达76×10–6F/cm2。     

低压铝箔交流腐蚀研究

在３０Ｈｚ频率下，通过铝箔在ＨＣｌ＋Ｈ２ＳＯ４＋ＨＮＯ３＋Ｈ３ＰＯ４体系中的交流腐蚀，研究腐蚀液组成中腐蚀主体及缓蚀剂对铝箔腐蚀的作用，探讨腐蚀过程中电源频率、腐蚀液温度、电流密度及腐蚀时间对铝箔腐蚀的影响。腐蚀液组成的配比恰当，有利于比容的提高。在特定的频率下采用合适的腐蚀液温度、适宜的电流密度和腐蚀时间可以提高铝箔的静电容量。     

基于硫醇-烯的微光学元件低收缩紫外压印工艺

基于硫醇-烯类材料具有固化凝胶点滞后的特点,本文将多种硫醇-烯类材料应用于紫外压印的连续浮雕结构微光学元件复制加工工艺中,用以降低固化收缩对于加工误差的影响。实验结果表明,虽然该材料的固化收缩达到13%,但加工结果的收缩误差优于2%。反应离子刻蚀实验表明,通过调节刻蚀气体含量,该材料可实现连续浮雕结构的等比例图形传递。研究结果表明,应用基于硫醇-烯材料的紫外压印工艺制作连续浮雕结构微光学元件是一种行之有效的方法。     

低压铝箔交流腐蚀工艺中的超声波辅助应用

采用国产铝箔,在超声波辅助条件下,对铝箔进行交流腐蚀,研究了超声波辅助腐蚀对腐蚀箔比容和力学性能的影响。结果发现:当腐蚀箔保持率为1.63g/dm2,采用磁力搅拌的腐蚀箔比容只有71.8×10–6F/cm2,而采用超声波辅助腐蚀的腐蚀箔比容为79.4×10–6F/cm2,提高了10.6%,且抗拉强度提高约20%。     

The effect of cathode materials on reactive ion etching of silicon and silicon dioxide in a CF4 plasma

Silicon and silicon dioxide have been Reactive Ion Etched in a CF₄ plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities to the RF cathode were between 0.1 and 1.0 W/cm². The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations for these experimental results will be discussed.     

特高压电容器用电极箔腐蚀工艺的研究

通过对特高压(Vfe=950V)电容器用电极箔微观形貌的理论计算,采用一次腐蚀控制孔密度和孔长度参数,二次腐蚀控制相应的孔径。研究了700～1100V特高压电极箔的两次电化学腐蚀工艺。使Vfe为950V的特高压电容器用电极箔的参数指标得到了优化:孔密度为0.116个/μm2,孔径为2.02μm,比容达到0.210×10–6F/cm2。     

A comparative study of wet and dry selective etching processes for GaAs/AIGaAs/lnGaAs pseudomorphic MODFETs

The etching characteristics of Al_xGa_1-xAs in citric acid/H₂O₂ solutions and SiCl₄/SiF₄ plasmas have been studied. Using a 4:1 solution of citric acid/H₂O₂ at 20° C, selectivities of 155, 260, and 1450 have been obtained for GaAs on Al_xGa_1-xAs withx = 0.3,x = 0.45, andx = 1.0, respectively. Etch rates of GaAs in this solution were found to be independent of line widths and crystal orientations for etched depths up to 1000?. GaAs etch profiles along [110] and [110] directions displayed different slope angles as expected. Selective reactive ion etching (SRIE) using SiCl₄/SiF₄ gas mixtures at 90 mTorr and -60 V self-biased voltage yielded selectivities between 200 and 500 forx values ranging from 0.17 to 1.0. SRIE etch rates for GaAs were relatively constant for etch depths of less than 1000?. At greater etch depths, etch rates varied by up to 76% for line widths between 0.3 and 1.0μm. Both selective wet etch and dry etch processes were applied to the fabrication of pseudomorphic GaAs/AIGaAs/lnGaAs MODFETs with gate lengths ranging from 0.3 to 2.5 μm on heterostructures with an embedded thin AlAs etch stop layer. A threshold voltage standard deviation of 13.5 mV for 0.3 μ gate-length MODFETs was achieved using a 4:1 citric acid/H₂O₂ solution for gate recessing. This result compares favorably with the 40 mV obtained using SRIE, and is much superior to the 230 mV achieved using the nonselective etch of 3:1:50 H₃PO₄: H₂O₂: H₂O. This shows that selective wet etching using citric acid/H₂O₂ solutions in conjunction with a thin Al_xGa_1-xAs(x ≥ 0.45) etch stop layer provides a reasonably simple, safe, and reliable process for gate recessing in the fabrication of pseudomorphic MODFETs.     

Controlling resist thickness and etch depth for fabrication of 3D structures in electron-beam grayscale lithography

In many applications such as optoelectronic devices, three-dimensional (3D) structures are required. Examples include photonic band gap (PBG) crystals, diffractive optical elements, blazed gratings, MEMS, NEMS, etc. It is known that the performance characteristics of such structures are highly sensitive to their dimensional fidelity. Therefore, it is essential to have a fabrication process by which such 3D structures can be realized with high dimensional accuracy. In this paper, practical methods to control thickness of the remaining resist and etch depth, which may be employed for fabrication of such 3D structures using grayscale electron-beam lithography, are described. Through experiments, explicit control of the remaining resist thickness and etch depth at the resolution of 20 nm for the feature sizes of 0.5 μm and 1 μm has been successfully demonstrated. Also, the 1:1 ratio of silicon to resist etching rates was achieved for transferring the remaining resist profile onto the silicon substrate.     

Characterization of Hg0.7Cd0.3Te n- on p-type structures obtained by reactive ion etching induced p- to n conversion

This paper presents transport measurements on both vacancy doped and gold doped Hg_0.7Cd_0.3Te p-type epilayers grown by liquid phase epitaxy (LPE), with N_A=2×10¹⁶ cm⁻³, in which a thin 2 μm surface layer has been converted to n-type by a short reactive ion etching (RIE) process. Hall and resistivity measurements were performed on the n-on-p structures in van der Pauw configuration for the temperature range from 30 K to 400 K and magnetic field range up to 12 T. The experimental Hall coefficient and resistivity data has been analyzed using the quantitative mobility spectrum analysis procedure to extract the transport properties of each individual carrier contributing to the total conduction process. In both samples three distinct carrier species have been identified. For 77 K, the individual carrier species exhibited the following properties for the vacancy and Au-doped samples, respectively, holes associated with the unconverted p-type epilayer with p ≈ 2 × 10¹⁶ cm⁻³, μ ≈ 350 cm²V⁻¹s⁻¹, and p ≈ 6 × 10¹⁵ cm⁻³, μ ≈ 400 cm²V⁻¹s⁻¹; bulk electrons associated with the RIE converted region with n ≈ 3 × 10¹⁵cm⁻³, μ ≈ 4 × 10⁴ cm²V⁻¹s⁻¹, and n ≈ 1.5 × 10¹⁵ cm⁻³, μ ≈ 6 × 10⁴ cm²V⁻¹s⁻¹; and surface electrons (2D concentration) n ≈ 9 × 10¹² cm⁻² and n ≈ 1 × 10¹³ cm⁻², with mobility in the range 1.5 × 10³ cm²V⁻¹s⁻¹ to 1.5 × 10⁴ cm²V⁻¹s⁻¹ in both samples. The high mobility of bulk electrons in the RIE converted n-layer indicates that a diffusion process rather than damage induced conversion is responsible for the p-to-n conversion deep in the bulk. On the other hand, these results indicate that the surface electron mobility is affected by RIE induced damage in a very thin layer at the HgCdTe surface.     

中高压阳极铝箔直流脉冲电蚀工艺及机理研究

用直流脉冲电源对高纯铝箔进行电化学侵蚀,研究了影响腐蚀箔性能的工艺参数条件,探索了隧道孔生长机理.结果表明:在硫酸和盐酸电解质体系中,影响腐蚀箔性能的工艺参数有直流脉冲电流密度、脉冲频率、占空比以及脉冲时间等;控制直流脉冲的电流密度峰值在0.8 A/cm2以上、脉冲电流单次通电延续时间在0.53 ms左右,能使铝箔产生纵横交错的隧道孔.