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1.
对低压铝箔施加五种不同波形交流电,研究了不同交流电波形对低压铝箔腐蚀形貌及电性能的影响。结果表明:正弦波、三角波电流变化率较小,孔大而浅,不易产生并孔;而方波、梯形波电流均有一段平稳不变期,易产生并孔;变形正弦波一个周期存在四个峰值电流,发孔几率比正弦波要大,也易出现并孔。实验表明如果在不同腐蚀阶段选择适当的波形和频率,会使电子铝箔的性能指标有较大提高。 相似文献
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G. Jäger-Waldau H. -U. Habermeier G. Zwicker E. Bucher 《Journal of Electronic Materials》1994,23(4):363-367
Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice
fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically
active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of
a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature
dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed
with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results. 相似文献
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S. Agarwala M. Tong D. G. Ballegeer K. Nummila A. A. Ketterson I. Adesida 《Journal of Electronic Materials》1993,22(4):375-381
The effects of selective reactive ion etching (SRIE) using SiCl4/SiF4 plasma on delta-doped GaAs/Al0.3Ga0.7As modulation-doped field-effect transistor (MODFET) structures and devices have been investigated. The results are compared
with those of corresponding conventionally doped MODFETs. Hall measurements were conducted at 300 and 77 K to characterize
the change in the transport properties of the two-dimensional electron gas due to low energy ion bombardment during the SRIE
process. Delta-doped structures showed a smaller change in sheet carrier density and mobility compared to conventionally doped
structures. Direct current and high frequency measurements were performed on the SRIE gate-recessed MODFETs. No significant
change in threshold voltage was observed for the delta-doped MODFETs in contrast to an increase of about 300 mV for the conventionally
doped MODFETs processed at a plasma self-bias voltage of −90 V and a 1200% overetch time. Maximum dc extrinsic transconductance
and unity current gain cutoff frequency did not change with SRIE processing for either of the structures.
This paper was presented at the Electronic Materials Conference at MIT, Cambridge, 1992. 相似文献
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Prakash N. K. Deenapanray C. S. Athukorala Daniel Macdonald W. E. Jellett E. Franklin V. E. Everett K. J. Weber A. W. Blakers 《Progress in Photovoltaics: Research and Applications》2006,14(7):603-614
This paper investigates the reactive ion etching of SiO2, Si3N4, and Si using CHF3/O2 plasma. In particular, we have characterized the time and rf power dependence of the carrier lifetimes in n‐ and p‐type FZ Si. The time dependence of reactive ion etching (RIE) at different rf powers provide insight into the two competing processes of damage accumulation and damage removal in the near‐surface region of the Si during plasma etching. The carrier lifetime, measured using the quasi‐steady‐state photoconductance (QSSPC) technique, has a quadratic dependence on the rf power, which can be related to changes in the dc self‐bias generated by the plasma at different rf powers. The change in carrier lifetime is similar in both n‐ and p‐type Si of the same doping concentration. Using this fact, together with the electronic properties of defects obtained by deep level transient spectroscopy (DLTS), we have modeled the injection‐dependence of the measured carrier lifetimes using the Shockley–Read–Hall model. The isochronal annealing behavior of plasma etched Si has also been studied. Copyright © 2006 John Wiley & Sons, Ltd. 相似文献
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Two reactive ion etchants, CF4 and SF6, have been compared in terms of plasma characteristics, silicon oxide etch characteristics, extent of RIE damage, and formation
of barrier layers on a GaAs surface after oxide etch. It was found that higher etch rates with lower plasma-induced dc bias
can be achieved with SF6 plasma relative to CF4 plasma and that this correlates with higher atomic fluorine concentration in SF6 plasma. RIE damage, measured by loss of sheet conductance in a thin highly-doped GaAs layer, could be modelled as a region
of deep acceptors at a high concentration in the conductive layer. By relating the sheet conductance change to the modelled
damaged layer thickness, it was found that the RIE-damaged thickness from both CF4 and SF6 plasmas had the same linear relation to plasma dc bias. Barriers to subsequent GaAs RIE were created during oxide overetch
at the GaAs surface. The barriers were identified by XPS as ∼20 A of GaF3 for CF4 plasma and ∼30 A of GaF3 on top of AsxSy for SF6 plasma. Ellipsometry was used to routinely determine the presence or absence of the barriers which could be removed in dilute
ammonia. 相似文献
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采用变频腐蚀工艺以及正交实验法,制备了铝电解电容器用低压铝箔,研究了腐蚀电源频率对所制低压铝箔腐蚀形貌及性能的影响。结果表明:腐蚀孔径随着电源频率的升高而变小,腐蚀电压随着频率升高而降低;频率25Hz为最佳工艺条件,所得腐蚀样品耐压值为83.2V,比容达16.07×10-6F/cm2。 相似文献
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低压铝箔交流腐蚀研究 总被引:2,自引:2,他引:2
在30Hz频率下,通过铝箔在HCl+H2SO4+HNO3+H3PO4体系中的交流腐蚀,研究腐蚀液组成中腐蚀主体及缓蚀剂对铝箔腐蚀的作用,探讨腐蚀过程中电源频率、腐蚀液温度、电流密度及腐蚀时间对铝箔腐蚀的影响。腐蚀液组成的配比恰当,有利于比容的提高。在特定的频率下采用合适的腐蚀液温度、适宜的电流密度和腐蚀时间可以提高铝箔的静电容量。 相似文献
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采用国产铝箔,在超声波辅助条件下,对铝箔进行交流腐蚀,研究了超声波辅助腐蚀对腐蚀箔比容和力学性能的影响。结果发现:当腐蚀箔保持率为1.63g/dm2,采用磁力搅拌的腐蚀箔比容只有71.8×10–6F/cm2,而采用超声波辅助腐蚀的腐蚀箔比容为79.4×10–6F/cm2,提高了10.6%,且抗拉强度提高约20%。 相似文献
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L. M. Ephrath 《Journal of Electronic Materials》1978,7(3):415-428
Silicon and silicon dioxide have been Reactive Ion Etched in a CF4 plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities
to the RF cathode were between 0.1 and 1.0 W/cm2. The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed
that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading
effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect
is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon
loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with
silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on
RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations
for these experimental results will be discussed. 相似文献
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M. Tong D. G. Ballegeer A. Ketterson E. J. Roan K. Y. Cheng I. Adesida 《Journal of Electronic Materials》1992,21(1):9-15
The etching characteristics of AlxGa1-xAs in citric acid/H2O2 solutions and SiCl4/SiF4 plasmas have been studied. Using a 4:1 solution of citric acid/H2O2 at 20° C, selectivities of 155, 260, and 1450 have been obtained for GaAs on AlxGa1-xAs withx = 0.3,x = 0.45, andx = 1.0, respectively. Etch rates of GaAs in this solution were found to be independent of line widths and crystal orientations
for etched depths up to 1000?. GaAs etch profiles along [110] and [110] directions displayed different slope angles as expected.
Selective reactive ion etching (SRIE) using SiCl4/SiF4 gas mixtures at 90 mTorr and -60 V self-biased voltage yielded selectivities between 200 and 500 forx values ranging from 0.17 to 1.0. SRIE etch rates for GaAs were relatively constant for etch depths of less than 1000?. At
greater etch depths, etch rates varied by up to 76% for line widths between 0.3 and 1.0μm. Both selective wet etch and dry
etch processes were applied to the fabrication of pseudomorphic GaAs/AIGaAs/lnGaAs MODFETs with gate lengths ranging from
0.3 to 2.5 μm on heterostructures with an embedded thin AlAs etch stop layer. A threshold voltage standard deviation of 13.5
mV for 0.3 μ gate-length MODFETs was achieved using a 4:1 citric acid/H2O2 solution for gate recessing. This result compares favorably with the 40 mV obtained using SRIE, and is much superior to the
230 mV achieved using the nonselective etch of 3:1:50 H3PO4: H2O2: H2O. This shows that selective wet etching using citric acid/H2O2 solutions in conjunction with a thin AlxGa1-xAs(x ≥ 0.45) etch stop layer provides a reasonably simple, safe, and reliable process for gate recessing in the fabrication of
pseudomorphic MODFETs. 相似文献
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J. Kim 《Microelectronic Engineering》2007,84(12):2859-2864
In many applications such as optoelectronic devices, three-dimensional (3D) structures are required. Examples include photonic band gap (PBG) crystals, diffractive optical elements, blazed gratings, MEMS, NEMS, etc. It is known that the performance characteristics of such structures are highly sensitive to their dimensional fidelity. Therefore, it is essential to have a fabrication process by which such 3D structures can be realized with high dimensional accuracy. In this paper, practical methods to control thickness of the remaining resist and etch depth, which may be employed for fabrication of such 3D structures using grayscale electron-beam lithography, are described. Through experiments, explicit control of the remaining resist thickness and etch depth at the resolution of 20 nm for the feature sizes of 0.5 μm and 1 μm has been successfully demonstrated. Also, the 1:1 ratio of silicon to resist etching rates was achieved for transferring the remaining resist profile onto the silicon substrate. 相似文献
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J. Antoszewski C. A. Musca J. M. Dell L. Faraone 《Journal of Electronic Materials》2000,29(6):837-840
This paper presents transport measurements on both vacancy doped and gold doped Hg0.7Cd0.3Te p-type epilayers grown by liquid phase epitaxy (LPE), with NA=2×1016 cm−3, in which a thin 2 μm surface layer has been converted to n-type by a short reactive ion etching (RIE) process. Hall and
resistivity measurements were performed on the n-on-p structures in van der Pauw configuration for the temperature range from
30 K to 400 K and magnetic field range up to 12 T. The experimental Hall coefficient and resistivity data has been analyzed
using the quantitative mobility spectrum analysis procedure to extract the transport properties of each individual carrier
contributing to the total conduction process. In both samples three distinct carrier species have been identified. For 77
K, the individual carrier species exhibited the following properties for the vacancy and Au-doped samples, respectively, holes
associated with the unconverted p-type epilayer with p ≈ 2 × 1016 cm−3, μ ≈ 350 cm2V−1s−1, and p ≈ 6 × 1015 cm−3, μ ≈ 400 cm2V−1s−1; bulk electrons associated with the RIE converted region with n ≈ 3 × 1015cm−3, μ ≈ 4 × 104 cm2V−1s−1, and n ≈ 1.5 × 1015 cm−3, μ ≈ 6 × 104 cm2V−1s−1; and surface electrons (2D concentration) n ≈ 9 × 1012 cm−2 and n ≈ 1 × 1013 cm−2, with mobility in the range 1.5 × 103 cm2V−1s−1 to 1.5 × 104 cm2V−1s−1 in both samples. The high mobility of bulk electrons in the RIE converted n-layer indicates that a diffusion process rather
than damage induced conversion is responsible for the p-to-n conversion deep in the bulk. On the other hand, these results
indicate that the surface electron mobility is affected by RIE induced damage in a very thin layer at the HgCdTe surface. 相似文献