Guest Editors' Introduction: New Dimensions in 3D Integration

Although various forms of 3D fabrication technology have existed for a few decades, only in recent years have researchers developed highly integrated 3D design technologies that are potentially manufacturable and economically feasible. Several companies are already marketing 3D structures built by wafer stacking, where the distance between the 3D layers on a wafer are on the order of the wafer thickness. But 3D technology must also surmount several challenges, such as exploiting the design space to build high-performance systems and architectures to gain the fullest advantage achievable. The articles in this special issue highlight these advances and challenges, providing an excellent snapshot of the state of 3D technology as it stands today.     

Guest Editors' Introduction: Opportunities and Challenges of 3D Integration

Interest in 3D integration is being renewed as researchers face challenges from the complexities, and cost, of scaling to 22 nm and beyond. Innovative device structures such as finFET, and extremely thin fully depleted silicon-on-insulator (ETSOI), must be deployed to continue scaling. Even with those structures, however, customary performance gains can no longer be achieved without also incurring an unacceptable increase in power. The cost of technology development in the nanoscale domain can run into the billions because massive lithographic retooling is required to cross the 22-nm barrier. The chip industry, therefore, is actively pursuing 3D integration as a viable alternative to provide density scaling. This special issue presents four articles on topics addressing some of these challenges.     

Guest Editors' Introduction

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