一种用于暗域交替式相移掩模设计的自适应版图划分方法

提出了一种新的用于加速130nm以下工艺交替式相移掩模设计流程的版图划分方法,该方法能够自适应调整版图划分的粒度.讨论了消除相位冲突的方法和版图压缩中相位兼容性保持的策略.利用上述算法实现的CAD原型系统经多个工业界例子的测试表明能够有效地适应随版图尺寸而快速增长的相位冲突复杂性,同时提供较好的PSM设计质量,并能满足不同求解精度和加速比的要求.     

一种用于暗域交替式相移掩模设计的自适应版图划分方法

提出了一种新的用于加速 1 30 nm以下工艺交替式相移掩模设计流程的版图划分方法 ,该方法能够自适应调整版图划分的粒度 .讨论了消除相位冲突的方法和版图压缩中相位兼容性保持的策略 .利用上述算法实现的 CAD原型系统经多个工业界例子的测试表明能够有效地适应随版图尺寸而快速增长的相位冲突复杂性 ,同时提供较好的 PSM设计质量 ,并能满足不同求解精度和加速比的要求     

先进相移掩模(PSM)工艺技术

先进相移掩模(PSM)制造是极大规模集成电路生产中的关键工艺之一,当设计尺寸(CD)为0.18μm时,就必须在掩模关键层采用OPC(光学邻近校正)和PSM(相移技术),一般二元掩模由于图形边缘散射会降低整体的对比度,无法得到所需要的图形。通过相位移掩模(PSM)技术可以显著改善图形的对比度,提高图形分辨率。相移掩模是在一般二元掩模中增加了一层相移材料,通过数据处理、电子束曝光、制作二次曝光对准用的可识别标记、二次曝光、显影、刻蚀,并对相移、缺陷等进行分析和检测,确保能达到设计要求。     

基于凸投影算法的多相位掩模设计原理研究

根据所需光刻图形的分布,反推掩模结构的思路,提出了一种基于交替投影算法的掩模设计方法。该方法设计出的掩模为振幅和相位连续。并给出了一个设计实例和量化方法。实验结果表明该方法对复杂相移掩模的设计有效,可以减小邻近效应。     

ULSI相移光刻技术＊

相移掩模光刻技术,是近几年来为了开发超大规模集成电路(ULSI)而发展起来的一种新颖光刻技术。它应用了光学相移掩模方法,大大提高了现有光学光刻设备的分辨率水平。本文综述了相移光刻技术的发展及其在ULSI中的应用。     

相移掩模清洗结晶控制

在高端集成电路制造方面,普通二元掩模已经不能满足晶圆使用要求。目前,高端(线宽0.18μm以下)集成电路生产主要采用相移掩模。相移掩模(Phase Shift Mask)制作过程中,掩模表面结晶(Haze)问题较难控制。为了控制和解决相移掩模表面结晶问题,提高成品率,主要讨论了不同的清洗工艺(Recipe)对相移掩模结晶的影响。然后通过实验验证了通过优化清洗工艺(Recipe),可以明显改善相移掩模表面结晶问题,达到控制相移掩模表面结晶的目的。     

i线相移掩模检查装置

为了采用曝光波长为０．３６５ｍ的光源制作０．３５－０．３０μｍ图形。采用了ｉ线步进方法，并研制了相移掩模。该掩模是由相移法构成图形，同时采用了光的干涉方法进行曝光形成微细图形，最重要的是相移器率和相移，其通过相移器的透过率与玻璃的透过率进行比较而测定，该测定重复性达±０．０５％，测定相移量应用微分干涉显微镜原理，为了获得高精度相移量，采用了条纹扫描干涉法，测定重复性达到±１°，相对应的模厚为±０．     

相移掩模的制作

本文阐述相移掩模技术研究中，常用的几种主要相移掩模制作方法，重点介绍了无络ＰＳＭ、Ｌｅｖｅｎｓｏｎ交替型ＰＳＭ、边级ＰＳＭ、亚分辨辅助ＰＳＭ以及激光直写制作ＰＳＭ的方法。     

相移掩模对曝光图形空间像光强分布影响的计算机模拟

本文讨论了提高曝光分辨率的一种主要方法：相移掩模方法。分析了相移掩模提高分辨率的原理，提出了相移掩模成像的模拟思想，推导了数学公式，并实现了计算机模拟，给出了一些初步结果。     

一种简单的衰减相移掩模

:本文介绍了一种与传统Cr掩模制作工艺相兼容的单层衰减相移掩模的结构、原理和制作方法 ,提供了部分实验结果。     

Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories

This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a non-cacheable memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm simultaneously finds a code layout for a cacheable region, a scratchpad region, and the other non-cacheable region of the address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23% without any performance degradation compared to the best result achieved by the conventional approach.     

100 nm分辨率交替式移相掩模设计

讨论了100nm分辨率交替式移相掩模设计中的关键问题,以及通过对版图的拓扑分析,建立自动化的解决相位冲突的各种方法。通过比较,确立了分层叠加曝光的方案,并针对分层叠加曝光技术,进行了100nm节点中分层技术中两种关键图形的模拟。得出了分层叠加曝光在100nm技术节点中也可以实现的结论。     

Cell-based interconnect migration by hierarchical optimization

Fueled by Moore's Law, VLSI market competition and economic considerations dictates the introduction of new processor's microarchitecture in a two-year cycle called “Tick-Tock” marketing strategy. A new processor is first manufactured in the most advanced stable process technology, followed in a one-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology, thus allowing higher production volumes, better performance and lower cost. Tick-Tock is enabled by the automation of chip's layout conversion from an older into a newer manufacturing process technology. This is a very challenging computational task, involving billions of polygons. We describe an algorithm of a hierarchy-driven optimization method for cell-based layout conversion used at Intel for already several product generations. It transforms the full conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full-chip problem does. The proposed algorithm preserves the design intent, its uniformity and maintainability, a key for the success of large-scale projects.     

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.     

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.     

Initializing RAM-based logarithmic processors

A logarithmic processor is proposed that uses external RAM for holding the table required for logarithmic subtraction. The proposed processor requires that the RAM be initialized before any computations occur. We give an algorithm to initialize the RAM using the limited arithmetic unit of the processor. The algorithm is ten times faster than a bit by bit computation of the logarithm and antilogarithm. Bounds are developed for comparing the error of this algorithm against the error of earlier algorithms. Simulation results show that this algorithm avoids catastrophic cancellation, and is as accurate as any previously known single precision algorith.     

异构多处理器系统的混合任务调度算法

针对实时异构系统的任务调度问题,提出了一种异构多处理器系统的混合实时任务调度算法.该算法采用带有非周期服务器的EDF( Earliest Deadline First)算法来调度单处理器上的任务集,可充分利用处理器的计算带宽.采用启发式搜索算法来进行任务的分配,以最大剩余计算带宽为搜索指标,可确保各处理器的负载尽量平衡...     

结合场景描述的文本生成图像方法

研究基于场景描述文本生成对应图像的方法,针对生成图像常常出现的对象重叠和缺失问题,提出了一种结合场景描述的生成对抗网络模型.首先,利用掩模生成网络对数据集进行预处理,为数据集中的对象提供分割掩模向量.然后,将生成的对象分割掩模向量作为约束,通过描述文本训练布局预测网络,得到各个对象在场景布局中的具体位置和大小,并将结果...     

SoC based floating point implementation of differential evolution algorithm using FPGA

This paper presents floating point design and implementation of System on Chip (SoC) based Differential Evolution (DE) algorithm using Xilinx Virtex-5 Field Programmable Gate Array (FPGA). The hardware implementation is carried out to enhance the execution speed of the embedded applications. Intellectual Property (IP) of DE algorithm is developed and interfaced with the 32-bit PowerPC 440 processor using processor local bus (PLB) of Xilinx Virtex-5 FPGA. In the proposed architecture the algorithmic parameters of DE are scalable. The software and hardware implementation of the DE algorithm is carried out in PowerPC embedded processor and hardware IP respectively. The optimization of numerical benchmark functions and system identification in control systems are implemented to verify the proposed hardware SoC platform. The performance of the IP is measured in terms of acceleration gain of the DE algorithm. The optimization problems are solved by using floating point arithmetic in both embedded processor and hardware. The experimental result concludes that the hardware DE IP accelerates the execution speed approximately by 200 times compared to equivalent software implementation of DE algorithm on PowerPC 440 processor. Further, as a case study an Infinite Impulse Response (IIR) based system identification task on SoC using the developed hardware accelerator is implemented.