一种10ps以下时钟偏差的纯数字电路分频器设计

本文对一款常用任意整数分频器进行改进,提出了一种纯数字、低时钟偏差、可获得任意整数分频结果的时钟分频器设计方案.该分频器由计数器与输出锁存器构成,通过调节逻辑结构与线延迟,完全平衡各时钟传播路径,大幅降低时钟偏差.仿真结果表明,在TSMC 0.13μm CMOS工艺下,当输入时钟频率在600MHz时,时钟偏差可控制在10ps以内.该分频器还包含自测电路,可判断时钟偏差是否满足要求.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

一种新的基于查找表的时钟性能驱动的增量式布局算法

提出了一种新的时钟性能驱动的增量式布局算法,它针对目前工业界较为流行的标准单元布局,应用查找表模型来计算延迟.由于在布局阶段较早地考虑到时钟信息,可以通过调整单元位置,更有利于后续的有用偏差时钟布线和偏差优化问题.来自于工业界的测试用例结果表明,该算法可以有效地改善合理偏差范围的分布,而对电路的其它性能影响很小.     

同步时钟偏差存在下的时差定位性能分析及改进的定位方法

同步时钟偏差会显著增加时差（TDOA）定位误差,该文针对这一问题进行了理论性能分析,并提出了改进方法.首先,分析了时钟偏差存在下参数估计方差的克拉美罗界（CRB）,给出了关于目标位置估计方差更为闭式的CRB表达式,随后基于最大似然（ML）估计准则和泰勒级数（TS）定位方法,定量推导了时钟偏差对于TDOA定位精度的影响.接着,提出了可抑制时钟偏差的降维TS定位方法,并且给出了时钟偏差的ML闭式解.最后,数值实验验证了文中理论分析的有效性,并且新方法可以有效抑制同步时钟偏差的影响.     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法,它综合了top-down和bottom-up两种时钟树拓扑产生方法,以最小时钟延时和总线长为目标,并把合理偏差应用到时钟树的构造中.电路测试结果证明,与零偏差算法比较,该算法有效地减小了时钟树的总体线长,并且优化了时钟树的性能.     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法 ,它综合了 top- down和 bottom- up两种时钟树拓扑产生方法 ,以最小时钟延时和总线长为目标 ,并把合理偏差应用到时钟树的构造中 .电路测试结果证明 ,与零偏差算法比较 ,该算法有效地减小了时钟树的总体线长 ,并且优化了时钟树的性能     

一种基站同步以太网时钟故障分析算法

在无线通信领域中,随着同步以太网时钟在基站上广泛应用,出现了大量与该时钟相关的时钟同步故障。针对这种情况,提出一种基于概率统计的故障分析算法。该算法通过分析基站时钟频率偏差变化数据的概率分布,结合基站时钟同步架构和器件特性,对故障点做出判断。该算法既能实现故障的远程分析定位,又能提前发现故障隐患。     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

基于机器学习方法的无线传感网络时钟同步算法

提出一种无线传感网络同步的方法,结合发送者-接收者同步(SRS)和接收者-接收者同步(RRS)两种方法,使得位于特定区域的传感器节点通过监听一对超级传感器节点交换时钟消息,借助最小二乘法精确估计出时钟偏差以及频率偏差进行补偿,实现节点间同步。该时钟同步方案的设计与其他已提出的同步方案相比,显著降低了整个网络的能量消耗而不引起任何同步精度的损失。     

一种非零偏差时钟网布线算法

特定的非零偏差时钟网比零偏差时钟网更具优势,它有助于提高时钟频率、降低偏差的敏感度.文章提出了一种新的非零偏差时钟树布线算法,它结合时钟节点延时和时钟汇点位置,得到一个最大节点延时次序合并策略,使时钟树连线长度变小.实验结果显示,这种算法与典型的最邻近选择合并策略相比较,可以减少20%～30%的总连线长度.     

Statistical skew modeling for general clock distribution networksin presence of process variations

Clock skew modeling is important in the performance evaluation and prediction of clock distribution networks. This paper addresses the problem of statistical skew modeling for general clock distribution networks in the presence of process variations. The only available statistical skew model is not suitable for modeling the clock skews of general clock distribution networks in which clock paths are not identical. The old model is also too conservative for estimating the clock skew of a well-balanced clock network that has identical but strongly correlated clock paths (for instance, a well-balanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock distributions, we propose a new approach to estimating the mean values and variances of both clock skews and the maximal clock delay of general clock distribution networks. Based on the new approach, a closed-form model is also obtained for well-balanced H-tree clock distribution networks. The paths delay correlation caused by the overlapped parts of path lengths is considered in the new approach, so the mean values and the variances of both clock skews and the maximal clock delay are accurately estimated for general clock distribution networks. This enables an accurate estimate of yields of both clock skew and maximal clock delay to be made for a general clock distribution network     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序.     

Iterative skew minimization for low swing clocks

This paper presents a new methodology that implements a low swing clock tree. For low power IC design, low swing clock trees are one of the known techniques to lower the overall power dissipation through decreasing the power consumption of the clock network, while trading off the clock skew, local timing (slack) and the variation-tolerance (due to decreased noise margin). In this paper, an iterative skew minimization scheme for low swing clock trees is proposed via in-place buffer sizing considering multiple process corners. The proposed approach can preserve the power savings of the low swing clock tree implementation across multiple process corners. The effect of the decreased clock swing on the local timing is analyzed: The degradation in the timing slack is shown to be insignificant due to bounded clock slew eliminating most of the timing degradation on the clock network or the logic paths induced by decreased clock swing. The experimental results show that the proposed methodology can achieve an average of up to 11% power savings, with a skew degradation of less than 5% compared to the original full-swing clock tree, satisfying a practical skew budget. The proposed scheme is highly practical as it only performs in-place buffer sizing on the original clock tree.     

A high-resolution synchronous mirror delay using successive approximation register

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-/spl mu/m 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.     

Analysis of the impact of process variations on clock skew

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V_T and I_DSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network     

Statistical clock skew modeling with data delay variations

Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate resources when optimizing global and local paths. Many published clock skew budgets neglect voltage jitter and process variation, which are becoming dominant factors in otherwise balanced H-trees. However, worst-case process variation assumptions are severely pessimistic. This paper describes the major sources of clock skew in a microprocessor using a modified H-tree and applies the model to a second-generation Itanium-M processor family microprocessor currently under design. Monte Carlo simulation is used to develop statistical clock skew budgets for setup and hold time constraints in a four-level skew hierarchy. Voltage jitter through the phase locked loop (PLL) and clock buffers accounts for the majority of skew budgets. We show that taking into account the number of nearly critical paths between clocked elements at each level of the skew hierarchy and variations in the data delays of these paths reduces the difference between global and local skew budgets by more than a factor of two. Another insight is that data path delay variability limits the potential cycle-time benefits of active deskew circuits because the paths with the worst skew are unlikely to also be the paths with the longest data delays     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time