Metastability tests of flip-flops in programmable digital circuits

This paper describes the methods and experimental techniques for determination of the metastability behavior of the flip-flops used in the programmable digital circuits. A dual model of the metastability distinguishes two transitions at the flip-flop output (L/H and H/L) which have different impact on the Mean Time Between Failures (MTBF) of the flip-flop. A new circuit of the late transition detector (LTD) allows for determination of the pairs of the metastability parameters, the window W and the time constant τ, for both transitions. The test results are presented for four types of programmable digital circuits fabricated commercially in CMOS technology. In the all tests, the H/L transition clearly dominates with respect to MTBF (as a worse one). The presented test methods can also be used for evaluation of flip-flops in nonprogrammable digital circuits.     

Metastability behavior of CMOS ASIC flip-flops in theory and test

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules     

Comments, with reply, on `Metastability of CMOS latch/flip-flop'

For the original article see ibid., vol.25, no.4, pp.942-951 (Aug. 1990). In the above titled paper L.-S. Kim and R.W. Dutton used SPICE small-signal circuit simulation (SPICE AC command) to evaluate a metastability performance parameter, τ, and compared several latch and flip-flop designs. They suggest that small-signal simulation is much easier to carry out than large-signal simulation for metastability studies and can be used to predict metastability performance. However, small-signal simulation is not sufficient to characterize metastability performance since it cannot determine a second parameter which is needed to determine synchronizer failure probability. In addition, Kim and Dutton make several errors in their use of small-signal simulation for determination of τ. The commenters present their own results that contrast with the original paper's conclusions, and discuss additional methods for determining τ. In their reply, Kim and Dutton acknowledge the commenters' points and go on to focus on how AC analysis can be used to extract the second parameter mentioned in the comment     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

Precise final state determination of mismatched CMOS latches

The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show that the final state depends on both initial voltages and latch mismatches. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight line (the metastable line) determines precisely the final latch state, and gives a very good insight about the mismatches which exist in the latch. Several SPICE simulation results are shown for matched/mismatched flip-flops. They agree well with the theoretical ones     

A synchronous approach for clocking VLSI systems

Presents a synchronous solution for clocking VLSI systems organized as distributed systems. This solution avoids the drawbacks of the self-timed approach. These VLSI systems are constituted of modules which represent synchronous areas driven by their own fast clock, interconnected by a synchronous communication mechanism driven by a slow clock. In order to avoid the risk of metastability in flip-flop between the modules and the communication mechanism, the author suggests to resynchronize the phase of each module clock on the transitions of the communication clock by a phase locked loop circuitry added to each module.     

Flash A/D转换器中火花码与亚稳态现象研究

全并行模数转换器(FlashA/D转换器)结构简单,转换速度快,但电路规模较大,精度受到限制.FlashA/D转换器具有"亚稳态","火花码"等非理想特性,严重的影响了它的工作性能.本文较系统地介绍和分析了已有的一些抑制"火花码"与"亚稳态"的方法.并提出一种基于概率统计的算法,通过SIMULINK软件进行仿真,对各种编码电路对输出误码率的影响进行了研究和量化对比,结论表明wlallace Trec编码结构对"火花码"及"亚稳态"的抑制能力最强.     

基于1-of-2共振隧穿数据选择器的可置位复位D触发器设计

文章以共振隧穿RT器件为主要器件,设计了上边沿触发的共振隧穿D触发器.该触发器以1-of-2共振隧穿数据选择器为核心电路,带预先置位和复位功能.此共振隧穿数据选择器电路的设计方法还能用于实现其他触发器电路,为采用基于RT器件设计触发器电路提供了一种新的并且有效简单的方法,弥补了共振隧穿电路中只能用MOBILE单元来设计时序电路的单一性,丰富了量子电路中触发器的类型.     

A flip-flop sensor array with on-spot A/D conversion

A two-dimensional optical flip-flop sensor array, consisting of an 8×8 matrix of flip-flop sensors integrated in one chip together with sense amplifiers and access selection circuitry, is discussed. A flip-flop sensor contains two phototransistors, one of which is covered over the aluminum while the other is exposed to light. Each flip-flop senses the light intensity and converts it to a series of ones and zeros. It is operated by turning the supply current on and off with a high frequency. During the absence of light the flip-flop is totally symmetrical and the number of ones and zeros is equal. Light causes an asymmetry in the flip-flop that changes the ratio of ones and zeros. A fully digital output is obtained by counting the number of ones. A triangle-wave voltage is applied to the flip-flop to vary its threshold. The device showed that a large array of sensors with on-spot A/D (analog-to-digital) conversion can be realized using the flip-flop sensor technique     

一种简单实用的差频方法原理研究及应用

介绍了D触发器差频的方法和应用条件,用最基础的时序分析的方法,对D触发器差频做一个理论上的验证,定量给出应用条件,并分析了产生误差的原因和最大的误差范围。同时,对这一方法的应用范围进行了拓展,给出了输入方波不对称时,对占空比限制的关系式。我们用软件仿真和试验结果验证了结论．并介绍了我们如何将D触发器差频方法用在湿度传感器的频率检测上。     

Calculation method to obtain worst-case static noise margins of logic circuits

A relatively simple calculation method is introduced using the flip-flop method, and by using the criterion that, with marginal static noise applied to the flip-flop, the loopgain is 1. As an example, the worst-case static series voltage noise margin of I2L is calculated.     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

All-optical flip-flop based on coupled laser diodes

An all-optical set-reset flip-flop is presented that is based on two coupled lasers with separate cavities and lasing at different wavelengths. The lasers are coupled so that lasing in one of the lasers quenches lasing in the other laser. The flip-flop state is determined by the laser that is currently lasing. A rate-equation based model for the flip-flop is developed and used to obtain steady-state characteristics. Important properties of the system, such as the minimum coupling between lasers and the optical power required for switching, are derived from the model. These properties are primarily dependent on the laser mirror reflectivity, the inter-laser coupling, and the power emitted from one of the component lasers, affording the designer great control over the flip-flop properties. The flip-flop is experimentally demonstrated with two lasers constructed from identical semiconductor optical amplifiers (SOAs) and fiber Bragg gratings of different wavelengths. Good agreement between the theory and experiment is obtained. Furthermore, switching over a wide range of input wavelengths is shown; however, increased switching power is required for wavelengths far from the SOA gain peak     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

Regenerative logic circuits with CMOS transistors

Logic circuits with transfer characteristics in the form of hysteresis, proposed in the paper, consist of two stages. The input stage is a standard CMOS logic circuit (inverter, NAND or NOR); the output stage is a simple flip-flop. The flip-flop consists of two inverters and one pair of CMOS transistors functioning as a resistor. The positive feedback loop is closed through these transistors. In the paper the most important static parameters and conditions of normal operation are analysed in detail.     

Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters

We present a theory for metastability error power in SuccessiveApproximation A/D converters. The traditional measure, BER, does not accountfor the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and aSignal-to-Metastability-error-Ratio, SMR, is suggested as a new measure. Suppressing SMR below SNR imposes a gain requirement on the comparator.     

FPGA设计中的亚稳态研究

探讨了亚稳态的产生机制,对FPGA设计中的亚稳态进行分析,针对FPGA设计中的亚稳态问题,给出了一系列行之有效的解决方法.提供的设计技巧和优化手段在实践中可以很好地抑制亚稳态,提高系统可靠性.     

Improved sense-amplifier-based flip-flop: design and measurements

Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 μm effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity