SINOMP:并行机互联网络通信性能模拟系统

研究并设计实现了并行机互联网络通信性能模拟系统——SINOMP。在单机系统上实现了互联网络的网络特征和通信过程的描述,提供路由选择和交换策略。通过指定目标系统的环境参数,获得目标系统互联网络在存储转发和虫蚀方式下的平均距离、吞吐率和以时钟周期为单位的通信时延,为并行机系统的研究和设计提供了直观、有效的工具。     

一种高速数字信号并行处理机的结构方案

现代数字满号处理技术对处理速度的要求越来越高，单个处理机已难以满足赛集运算的速度要求．本文在采用并行机虚拟实现神经网络的应用背景下，简要介绍了TMS320C40的待点和用它为成并行处理机时并行机系统拓扑结构上的优化考虑．     

小麦植株拓扑结构发生过程的仿真研究

以小麦作物为研究对象,采用小麦植株形态结构的观测分析,提出了由多层次自动机模型、植株拓扑结构数据模型和模型调度算法构成的小麦植株拓扑结构的发生过程仿真方法.多层次自动机模型将小麦植株拓扑结构的发展过程视为生长单元、叶元和器官三个不同层次基本结构的重复、迭代,并以此建立宏状态、子状态和微状态自动机,进行拓扑结构演变过程的控制和形式化描述;植株拓扑结构数据模型基于小麦分枝结构的特征,建立拓扑结构的抽象单元和抽象单元间的关系,实现植株拓扑结构的描述与结构化存储;模型调度算法以多层次自动机为控制机制,进行植株拓扑结构数据的动态更新.在此基础上,采用VC++/OpenGL建立小麦虚拟生长可视化系统,进行了植株拓扑结构发生过程仿真,结果表明,改进方法能够对小麦个体全生育期拓扑结构的演变过程进行准确仿真,与同类仿真方法相比较,具有拓扑发生规律形式化定义易于建模理解、拓扑结构发生仿真控制精确、拓扑控制与描述分离利于改进和扩展等特点,可为虚拟小麦生长研究提供技术支撑.     

一类层次双环网络的构造及其路由算法

高效互联网络的拓扑结构一直是人们关注的热点问题。提出了一类层次双环互联网络HDRN（k）,给出了HDRN（k）网络的构造方法,研究了它的性质,并且通过与相关网络的比较,证实了HDRN（k）具有好的连接性、短的直径以及简单的拓扑结构,是一种实用的互联网络。另外,讨论了HDRN（k）网络的路由性质,设计了点点路由和Broadcast路由算法,证明了这两种路由算法的通信效率与层次环网络上对应算法的通信效率相比均有明显的提高。综上所述,HDRN（k）是一种具有良好拓扑性质的新型互联网络。     

FI代数上的一致拓扑空间

拓扑结构是逻辑代数中一个重要的研究内容。为描述Fuzzy蕴涵代数的拓扑结构,利用滤子诱导的同余关系在FI代数上构造一致结构和一致拓扑,证明了导出的一致拓扑空间是不连通的、零维的、局部紧的、完全正则的第一可数空间,是[T0]空间当且仅当诱导它的滤子为{1},且FI代数中的蕴涵运算关于导出的一致拓扑是连续的。此外,讨论了商空间的性质。这对从拓扑层面去揭示FI代数的内部结构具有促进作用。     

基于并行冗余协议的网络拓扑快速发现方法

针对冗余以太网网络拓扑发现的实时性问题,提出一种基于并行冗余网络协议的网络拓扑结构快速发现方法,包括在网络管理端根据网络需求,发送拓扑发现请求报文,端系统设备在接收到请求之后周期性地向管理端发送拓扑发现报文,管理端根据接收到的报文信息进行运算,从而得到网络的拓扑结构。通过OMNET++网络仿真软件进行仿真验证,结果表明,该方法的网络拓扑构建时间维持在 60 ms,并且实现了与简单网络管理协议的兼容。     

贪婪算法之拓扑排序的实现

拓扑排序是图的应用领域中一种重要运算,可以根据拓扑序列串行地安排活动。本文给出了拓扑排序的贪婪算法．讨论了算法中用到的数据结构．本文采用邻接袁和栈以C＋＋语言进行仿真．给出了仿真结果。     

双环Petersen网络直径公式及最优路由算法

双环Petersen图互联网络DLCPG(k)是双环网络与Petersen图的笛卡尔积,它具有良好的可扩展性、较短的网络直径和简单的拓扑结构等特性。通过研究其拓扑结构,得到了DLCPG(k)直径的显式公式,并给出了该网络的最优单播路由算法。     

L-系统在植物仿真中的应用研究

L-系统(L-system)是以形式化的语言描述植物的结构和生长,将其引入到植物图形仿真的研究中,能简洁且逼真地描述植物的拓扑结构,生成包括叶片、枝条和化序等植物形态.     

基于拓扑结构的蠕虫防御策略仿真分析

提出了基于拓扑结构控制的蠕虫防御策略,并通过构建仿真模型对其进行了仿真验证分析.首先对蠕虫传播所依赖的拓扑结构的主要形式进行了分析,提出了相应的生成算法,并对算法的有效性进行了验证;随后提出了三种拓扑结构控制策略仿真模型;最后分别对这三种策略在不同拓扑结构下的蠕虫传播控制性能进行了仿真实验.实验结果证明:通过适当地控制拓扑结构,可以有效地遏制拓扑相关蠕虫传播.     

A Virtual Ring Method for Building Small-World Structured P2P Overlays

This paper presents a general virtual ring method to design and analyze small-world structured P2P networks on the base topologies embedded in ID spaces with distance metric. Its basic idea is to abstract a virtual ring from the base topology according to the distance metric, then build small-world long links in the virtual ring and map the links back onto the real network to construct the small-world routing tables for achieving logarithmic greedy routing efficiency. Four properties are proposed to characterize the base topologies that can be turned into small-world by the virtual ring method. The virtual ring method is applied to the base topologies of d-torus with Manhattan distance, high dimensional d-torus base topologies, and other base topologies including the unbalanced d-torus and the ring topology with tree distance. Theoretical analysis and simulation experiments demonstrate the efficiency and the resilience of the proposed overlays.     

Parallel computer vision on a reconfigurable multiprocessor network

A novel reconfigurable architecture based on a multiring multiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain 2D mesh topologies of varying sizes and also a single one factor of the Boolean hypercube in any given configuration. A large class of algorithms for the 2D mesh and the Boolean n-cube are shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low and intermediate level computer vision such as the FFT, edge detection, template matching, and the Hough transform. Timing results for typical low and intermediate level vision algorithms on a transputer based prototype are presented     

The backpropagation algorithm on grid and hypercube architectures

In this paper, we first describe a model for mapping the backpropagation artificial neural net learning algorithm onto a massively parallel computer architecture with a 2D-grid communications network. We then show how this model can be sped up by hypercube inter-processor connections that provide logarithmic time segmented parallel prefix operations. This approach can serve as a general model for implementing algorithms for layered neural nets on any massively parallel computers that have 2D-grid or hypercube communication networks.

We have implemented this model on the Connection Machine CM-2 — a general purpose, massively parallel computer with a hypercube topology. Initial tests show that this implementation offers about 180 million interconnections per second (IPS) for feed-forward computation and 40 million weight updates per second (WUPS) for learning. We use our model to evaluate this implementation: what machine-specific features have helped improve the performance and where further improvements can be made.     

MLMIN: A multicore processor and parallel computer network topology for multicast

In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.     

RTS: A system to simulate the real time cost behaviour of parallel computations

In this paper, we present a software tool, RTS (real time simulator), that analyses the time cost behaviour of parallel computations through simulation. It is assumed in RTS that the computer system which supports the executions of parallel computations has a limited number of processors all processors have the same speed and they communicate with each other through a shared memory. In RTS, the time cost of a parallel computation is defined as a function of the input, the algorithm, the data structure, the processor speed, the number of processors, the processor power allocation, the communication and the execution environment. How RTS models the time cost is first discussed in the paper. In the model, a locking technique is used to manipulate the access to the shared memory, processing power is equally allocated among all the operations that are currently being performed in parallel in the computer system, and the number of operations in the execution environment of a parallel computation changes from time to time. How RTS works and how the simulation is used to do time cost analysis are also discussed.     

Propagation modeling of active P2P worms based on ternary matrix

Propagation modeling of worms has become an attractive research field in recent years since it facilitates worm prediction, detection, analysis and prevention etc. In this work, we propose a novel ternary-matrix-based model to describe the propagation trend of active P2P worms. Compared to existing logic-matrix-based models, our model takes the time lags into consideration by introducing new states and special matrix operations. Our model is easy of derivation and deployment because it confines derivation process to pure matrix operations. Moreover, two other advantages of our model are fully explored. One is expressiveness: (1) practical P2P topology can be modeled in the topology matrix; (2) the state of any node can be identified at any time; (3) and the attack path of any node can be backtracked in linear time. Flexibility is the other merit: our model can adapt to different scenes by changing the related parameters, particularly our model is general for different kinds of time lags and P2P topologies.     

Parallel program debugging by specification

Most message passing parallel programs employ logical process topologies with regular characteristics to support their computation. Since process topologies define the relationship between processes, they present an excellent opportunity for debugging. The primary benefit is that process behaviours can be correlated, allowing expected behaviour to be abstracted and identified, and undesirable behaviour reported. However, topology support is inadequate in most message passing parallel programming environments, including the popular Message Passing Interface (MPI) and the Parallel Virtual Machine (PVM). Programmers are forced to implement topology support themselves, increasing the possibility of introducing errors. This paper proposes a trace‐ and topology‐based approach to parallel program debugging, driven by four distinct types of specifications. Trace specifications allow trace data from a variety of sources and message passing libraries to be interpreted in an abstract manner, and topology specifications address the lack of explicit topology knowledge, whilst also facilitating the construction of user‐consistent views of the debugging activity. Loop specifications express topology‐consistent patterns of expected trace events, allowing conformance testing of associated trace data, and error specifications specify undesirable event interactions, including mismatched message sizes and mismatched communication pairs. Both loop and error specifications are simplified by having knowledge of the actual topologies being debugged. The proposed debugging framework enables a wealth of potential debugging views and techniques. Copyright © 2004 John Wiley & Sons, Ltd.     

Mapping Parallel Application Communication Topology to Rhombic Overlapping-Cluster Multiprocessors

This paper extends research into rhombic overlapping-connectivity interconnection networks into the area of parallel applications. As a foundation for a shared-memory non-uniform access bus-based multiprocessor, these interconnection networks create overlapping groups of processors, buses, and memories, forming a clustered computer architecture where the clusters overlap. This overlapping-membership characteristic is shown to be useful for matching parallel application communication topology to the architecture's bandwidth characteristics. Many parallel applications can be mapped to the architecture topology so that most or all communication is localized within an overlapping cluster, at the low latency of processor direct to cache (or memory) over a bus. The latency of communication between parallel threads does not degrade parallel performance or limit the graininess of applications. Parallel applications can execute with good speedup and scaling on a proposed architecture which is designed to obtain maximum advantage from the overlapping-cluster characteristic, and also allows dynamic workload migration without moving the instructions or data. Scalability limitations of bus-based shared-memory multiprocessors are overcome by judicious workload allocation schemes, that take advantage of the overlapping-cluster memberships. Bus-based rhombic shared-memory multiprocessors are examined in terms of parallel speedup models to explain their advantages and justify their use as a foundation for the proposed computer architecture. Interconnection bandwidth is maximized with bi-directional circular and segmented overlapping buses. Strategies for mapping parallel application communication topologies to rhombic architectures are developed. Analytical models of enhanced rhombic multiprocessor performance are developed with a unique bandwidth modeling technique, and are compared with the results of simulation.     

一种用于网格服务部署的拓扑模型

网格可以看成是一种新兴的基础设施,它为大型的网络服务提供相应的资源支持,即组织大规模分布式的资源,包括计算能力、存储资源和带宽等。网格需要解决网络的异构性、动态性和伸缩性等问题,尤其是网格服务的部署;而网格服务部署的关键是网络拓扑。文中提出了一种用于网格服务部署的拓扑模型。该模型有明显的简单性,且具有动态的、可伸缩的特点,也考虑到了网络的异构性,可以描述那些有不对称链路、防火墙、非IP网络、非分层拓扑等复杂情况的网络拓扑。同时还给出了相应的XML描述。     

Fault-tolerant de Bruijn and shuffle-exchange networks

This paper addresses the problem of creating a fault-tolerant interconnection network for a parallel computer. Three topologies, namely, the base-2 de Bruijn graph, the base-m de Bruijn graph, and the shuffle-exchange, are studied. For each topology an N+k node fault-tolerant graph is defined. These fault-tolerant graphs have the property that given any set of k node faults, the remaining N nodes contain the desired topology as a subgraph. All of the constructions given are the best known in terms of the degree of the fault-tolerant graph. We also investigate the use of buses to reduce the degrees of the fault-tolerant graphs still further