Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

一种高性能CMOS单片中频接收机

研制了一种CM O S低压低功耗中频接收机芯片,它包含混频器、限幅放大器、解调器以及场强指示、消音控制等模块,可用于短距离的FM/FSK信号的接收和解调。该接收机采用1st s ilicon 0.25μm CM O S工艺,芯片的测试结果表明整机接收灵敏度为-103 dBm,最高输入射频频率可以达到100 MH z,解调器的线性解调范围为±10 kH z,典型鉴频灵敏度为40 mV/kH z,输入FM信号(调频指数3,信号频率1 kH z)时解调信号的SFDR为41.3 dB。芯片的工作电源电压范围为2~4 V,工作电流3 mA,有效面积0.25 mm2。     

A high-IP3 RF receiver chip set for mobile radio base stations upto 2 GHz

We present a monolithically integrated high third-order intercept point (IP3) radio frequency (RF) receiver chip set for mobile radio base stations up to 2 GHz, in a 25-GHz f_T Si bipolar production technology. The chip set consists of a RF preamplifier, active mixer circuits, and an intermediate frequency (IF) limiter. The preamplifier gain is 12 dB, the noise figure is 5.5 dB at 900 MHz, and the output (OIP3) is up to +24 dBm depending on supply voltage. The two different mixers provide a conversion gain of 1.5 dB up to 3 dB, an OIP3 in the range of +21 dBm up to +29 dBm, and a minimal single sideband (SSB) noise figure of 13 dB. The IF limiter shows an excellent limiting characteristic at 10 dBm output power and has a high bandwidth of more than 1 GHz     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

An Ultra-Wideband Distributed Active Mixer MMIC in 0.18-μm CMOS Technology

In this paper, a distributed circuit topology for active mixers suitable for ultra-wideband operations is presented. By employing nonuniform artificial transmission lines with the complementary transconductance stages in the Gilbert-cell multiplier, the proposed mixer demonstrates broadband characteristics at microwave frequencies while maintaining a high conversion gain (CG) with improved gain flatness. Using a 0.18-mum CMOS process, the proposed circuit is implemented, exhibiting a -3-dB bandwidth of 28 GHz. With a local-oscillator power of 3 dBm and an IF frequency of 10 MHz, the fabricated circuit has a CG of 12.5plusmn1 dB and an average input third-order intercept point (IIP₃) of 0 dBm within the entire frequency range. The fully integrated wideband mixer occupies a chip area of 0.87times0.82 mm² and consumes a dc power of 20 mW from a 2-V supply voltage     

A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering

A CMOS wideband front-end IC is demonstrated in this paper.It consists of a low noise transconductance amplifier（LNTA） and a direct RF sampling mixer（DSM） with embedded programmable discrete-time filtering.The LNTA has the features of 0.5-6 GHz wideband,wideband input matching and low noise.The embedded filter following the DSM operates in discrete-time charge domain,filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency.The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz.It shows a conversion gain of 12.6 dB and IP_1dB of-7.5 dBm at 2.4 GHz.It occupies a chip area of 0.23 mm² and consumes 14 mA DC current.     

采用内嵌了离散时间滤波器的射频直接采样混频器的CMOS宽带前端芯片

本文展示了一种新型的CMOS宽带射频前端芯片。它由低噪声跨到放大器（LNTA）和内嵌了可编程的离散时间滤波器的射频直接采样混频器（DSM）组成。第一级的LNTA具有0.5到6GHz的带宽,宽带输入匹配以及低噪声的特性。DSM之后的内嵌滤波器工作在离散时间电荷域,可以根据始终频率控制中频带宽,同时滤除混叠和干扰信号。测试结果显示,在0.5到6GHz的带宽内,噪声系数均低于7dB。在2.4GHz处,转换增益为12.6dB,IP1dB为-7.5dBm。该芯片所占面积为0.23mm2,消耗14mA直流电流。     

An I/Q-Channel Time-Interleaved Bandpass Sigma–Delta Modulator for a Low-IF Receiver

This brief proposes a multiplexing scheme to realize an I/Q-channel time-interleaved (TI) bandpass sigma-delta modulator that shares operational transconductance amplifiers to minimize power consumption and silicon area for a low-intermediate-frequency (IF) wireless receiver. The test chip was fabricated for a 10.7-MHz IF system with a 0.35-mum CMOS process. The measured peak signal-to-noise distortion ratio for a 200-kHz bandwidth is approximately 73 dB. The power consumption of the fabricated chip is 61 mW with a 3.3-V supply, and the silicon area is 1.78 mm². The measured channel crosstalk is about -48 dB     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 71-MHz CMOS IF-baseband strip for GSM

An intermediate-frequency (IF) baseband strip for a superheterodyne GSM receiver developed in a 0.25-μm CMOS technology is presented. It contains a 71-MHz IF amplifier, programmable between -20 and +60 dB in 2-dB steps; a quadrature demodulator; and two low-pass output filters for channel selection. Measurements show an overall maximum gain of 89 dB and a noise figure of 3.8 dB. Phase and amplitude mismatches of the demodulator are below 10 and 0.1 dB, respectively. The high linearity required by the blocking and intermodulating signals, which are not completely suppressed by the IF filter, has been achieved using 4.7 mA from the 2,5-V power supply     

一种低闪烁噪声高线性度WLAN混频器的设计

提出一种适用于零中频接收的WLAN混频器,采用折叠结构降低开关对的偏置电流,以得到良好的闪烁噪声性能;通过在混频器的驱动级引入辅助管,并优化其衬底电压和尺寸来抵消跨导管的非线性,进而提升电路的线性度.利用Volterra级数辅助分析制约线性度特性的限制因素.基于Chartered O.18 μm CMOS工艺的Spectre-RF仿真表明,电路在WLAN的2.4 GHz频段具有良好的电学性能,噪声系数为8.6 dB,闪烁噪声角为105 kHz,IIP3为5.8 dBm,芯片整体功耗为10 mW,核心电路占用面积为0.09 mm2.     

A low distortion bipolar mixer for low voltage direct up-conversionand high IF systems

This paper describes the implementation of a low distortion mixer for direct up-conversion and high IF systems. A Gilbert cell with a low distortion transconductance constitutes the mixer core. A current feedback loop is used to linearize the transconductance stage, achieving an alternate channel leakage of -71 dBc with a power penalty of 15%. The mixer operates from 2.7 to 7.5 V of supply voltage and over a temperature range of -40 to 85°C. It provides -3 dBm output power while drawing 7.5 mW from a 3-V supply. The mixer is implemented in 1-μm BiCMOS for a global system for mobile communications (GSM) chip set     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit     

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

This paper presents a fully integrated 0.18-/spl mu/m CMOS Bluetooth transceiver. The chip consumes 33 mA in receive mode and 25 mA in transmit mode from a 3-V system supply. The receiver uses a low-IF (3-MHz) architecture, and the transmitter uses a direct modulation with ROM-based Gaussian low-pass filter and I/Q direct digital frequency synthesizer for high level of integration and low power consumption. A new frequency shift keying demodulator based on a delay-locked loop with a digital frequency offset canceller is proposed. The demodulator operates without harmonic distortion, handles up to /spl plusmn/160-kHz frequency offset, and consumes only 2 mA from a 1.8-V supply. The receiver dynamic range is from -78 dBm to -16 dBm at 0.1% bit-error rate, and the transmitter delivers a maximum of 0 dBm with 20-dB digital power control capability.     

InAlAs/InGaAs HBT X-band double-balanced upconverter

We report on an InAlAs/InGaAs HBT Gilbert cell double-balanced mixer which upconverts a 3 GHz IF signal to an RF frequency of 5-12 GHz. The mixer cell achieves a conversion loss of between 0.8 dB and 2.6 dB from 5 to 12 GHz. The LO-RF and IF-RF isolations are better than 30 dB at an LO drive of +5 dBm across the RF band. A pre-distortion circuit is used to increase the linear input power range of the LO port to above +5 dBm. Discrete amplifiers designed for the IF and RF frequency ports make up the complete upconverter architecture which achieves a conversion gain of 40 dB for an RF output bandwidth of 10 GHz. The upconverter chip set fabricated with InAlAs/InGaAs HBT's demonstrates the widest gain-bandwidth performance of a Gilbert cell based upconverter compared to previous GaAs and InP HBT or Si-bipolar IC's     

An Active IF Balun for a Doubly Balanced Resistive Mixer

In this letter, we present a wideband active intermediate frequency (IF) balun for a doubly balanced resistive mixer implemented using a 0.5 mum GaAs pHEMT process. The 0.3 times 0.5 mm² IF balun was realized through a DC-coupled differential amplifier in order to extend IF frequency of the mixer to DC. The measured amplitude and phase imbalances were less than 1 dB and 5deg, respectively, from DC to 7 GHz. The output third order intercept (OIP3) and P1 dB of the IF balun were 18 dBm and 6 dBm, respectively at 1 GHz. The mixer with the IF balun is 1.7 times 1.8 mm² in size, has a conversion loss of 2 to 8 dB from 8 to 20 GHz RF frequency at a fixed IF of 1 kHz, which proves the mixer operates successfully at an IF frequency close to DC. The measured OIP3 were +10 to +15 dBm over the operating frequency with a DC power consumption of 370 mW.