硅基HgCdTe光伏器件的暗电流特性分析

对硅基HgCdTe中波器件进行了变温电流电压特性的测试和分析。测量温度从30K到240K，得到R0对数与温度的1000／T的实验曲线及拟合结果。同时选取60K、80K及110K下动态阻抗R与电压V的曲线进行拟合分析。研究表明在我们器件工作的温度点80K，零偏压附近主要的电流机制是产生复合电流和陷阱辅助隧穿电流。要提高器件的水平，必须降低陷阱辅助隧穿电流和产生复合电流对暗电流的贡献。     

Electrical properties and transport mechanisms of InP/InGaAs HBTsoperated at low temperature

The electrical properties of InP/InGaAs HBTs have been comprehensively investigated between room and near liquid helium temperature. Physical mechanisms for the devices operated in different temperature ranges have been clearly identified. The low temperature measurements indicate that, in the temperature range of 240 K to 300 K, the base current is dominated by electron-hole band-to-band recombination; in the temperature range 77 K to 240 K, trap-related recombination (Shockley-Read-Hall recombination) plays an important role in determining base current; and for temperature lower than 77 K, the collector and base currents are found to be limited by electron tunneling through the barrier formed by the conduction-band discontinuity at the E-B junction. These findings provide us with better physical insight of the device operation at low temperature, which is particularly important for the optimization of InP HBT technology for low temperature applications as well as the development of a quantitative model for circuit design     

Correlation of tunnelling currents and tunable luminescence in selectively diffused nipi LEDs

Measurements of the current/voltage characteristics and electroluminescence spectra of nipi LEDs with selectively diffused contacts have been performed over the temperature range 3-300 K. Good correlation has been observed between the forward characteristics of the diodes and the tuning of the electroluminescence. Analysis of the I/V characteristics indicates that the recombination occurs by electron tunnelling through the parabolic potential barriers.<>     

Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V_II and V_IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V _H-V_I, and V_IH-V _II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β_N/β_P ratio as the temperature is lowered     

Transport and electroluminescence mechanism in Au/（Si/ SiO2）/P-Si film

Following the development of information technolo-gy,it has been a tendency to take the place of electronby photon as a carrier of information,since photons canmove thousands ti mes faster than electrons ,which cani mprove the rate of communication.Silico…     

Quantum-well resonant tunneling bipolar transistor operating at room temperature

The first resonant tunneling bipolar transistor (RBT) is reported. The AlGaAs/GaAs wide-gap emitter device, grown by molecular beam epitaxy (MBE), contains a GaAs quantum well and two AlAs barriers between the emitter and the collector. In the common emitter configuration, when the base current exceeds a threshold value, a large drop in the collector current (corresponding to a quenching of the current gain β) is observed at room temperature, along with a pronounced negative conductance as a function of the collector-emitter voltage. These striking characteristics are caused by the quenching of resonant tunneling through the double barrier as the conduction band edge in the emitter is raised above the bottom of the first quantized subband of the well. Single-frequency oscillations are observed at 300 K. The inherent negative transconductance of these new functional devices is extremely valuable for many logic and signal processing applications.     

A novel SOI MOSFET electrostatic field sensor

A novel low temperature solid state electric field sensor is demonstrated as a promising sensor. The sensor is a type of constant voltage Wheatstone bridge whose resistors are four direct gate SOI MOSFET devices. It is demonstrated in theory that the output voltage signal is proportional to the electric field E, the temperature drift is about zero when the temperature is in the range from 200 to 400 K, and the doping concentration is in the range from 1×1014 to 1 × 1016 cm-3. The experiment results indicate that the resolution of the sensor is about 3.27 mV for a 1000 V/m electric field at 300 K, and the voltage drift by an amount is about 47 V/m field signal when the degree temperature is in the range from 300 to 370 K, which is much smaller than the current drift of a single MOSFET which is about 10000 V/m field signal.     

一种新型MOSFET静电场传感器

本文提出了一种非常有发展前途的低温漂固态电场传感器。此传感器是一种恒压惠斯顿电桥,它的电阻是由四个直接栅极SOI MOSFET器件。理论上证明这种传感器的输出信号电压与测量电场成正比,温度漂移等于零。实验结果表明,在300K温度下,传感器的分辨率为3.27 mV/KV/m,大气环境下的温度漂移相当于47V/m的电场,其远小于大气温度下相当于10,000V/m的电流漂移。     

Performance Evaluation of Field-Enhanced P-Channel Split-Gate Flash Memory

A p-channel split-gate Flash memory cell, employing a field-enhanced structure, is investigated in this letter. A cell with a sharp poly-tip structure is utilized to enhance the electric field, while using Fowler–Nordheim tunneling through the interpoly oxide. The cell demonstrated an erase voltage as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of$sim$2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300 k program/erase cycles.     

Accurate Simulation of Temperature-Dependent Dark Current in HgCdTe Infrared Detectors Assisted by Analytical Modeling

Resistance–voltage curves of n ⁺-on-p Hg_1−x Cd _x Te infrared photodiodes were measured in the temperature range of 60 K to 120 K. Characteristics obtained experimentally were fitted by an improved simultaneous-mode nonlinear fitting process. Based on the extracted parameters, an efficient numerical sim- ulation approach has been developed by inserting trap-assisted and band-to-band tunneling models into continuity equations as generation–recombination processes. Simulated dark-current characteristics were found to be in good agreement with the experimental data, demonstrating the validity of the nonlinear fitting process. Our work presents an efficient method for dark-current simulations over a wide range of temperatures and bias voltages, which is important for investigating mechanisms of carrier transport across the HgCdTe junction.     

Study of photoluminescence and electroluminescence mechanisms in quantum-confined InSb/InAs heterostructures

Photoluminescence and electroluminescence in InSb/InAs heterostructures with ultrathin InSb insertions grown by molecular-beam epitaxy have been systematically studied. Measurements were made in the temperature range from 2 to 300 K on a large set of samples of various designs, with both the InAs matrix and ultrathin InSb insertions grown by different methods. The primary goal of the study was to identify the main radiative recombination channels in these heterostructures. It is shown that optical transitions associated with acceptor impurity centers in the InAs matrix represent an important mechanism diminishing the efficiency of luminescence from InSb insertions at room temperature. The results obtained are important for development of optimal growth modes and design of the active region of light-emitting devices based on quantum-confined InSb/InAs structures emitting in the range 3–5 μm.     

Tunnel diode reverse characteristics at different temperatures

The tunnel diode characteristics in the reverse direction at low and high temperatures is investigated applying a simplified model of the heavily doped semiconductor junction. In this model momentum is conserved and a calculation of the tunneling probability is made on account of field and image-charge effects on the potential energy barrier.The energy gap of heavily doped germanium is plotted as a function of the impurity concentration at 78 and 300 K. It is suggested that the tunneling current increases with concentration for a given temperature, and with temperature for a given concentration.Our theoretical results are in good agreement with the experiments. The breakdown voltage decreases with temperature for a given reverse current. Finally it is suggested that the tunneling current in the Kane's theory is much larger compared to that given in the present theory and experiments.     

Temperature dependence of InAs/GaAs quantum dots solar photovoltaic devices

This paper presents the temperature dependence measurements characterisation of several InAs/GaAs quantum dots （QDs） solar cell devices. The devices with cylindrical geometry were fabricated and characterised on-wafer under 20 suns in a temperature range from 300°K to 430°K. The temperature dependence parameters such as open circuit voltage, short circuit density current, fill factor and efficiency are studied in detail. The increase of temperature produces an enhancement of the short circuit current. However, the open circuit voltage is degraded because the temperature increases the recombination phenomena involved, as well as reducing the effective band gap of the semiconductor.     

Current-voltage characteristics of high current density siliconEsaki diodes grown by molecular beam epitaxy and the influence ofthermal annealing

We present the characteristics of uniformly doped silicon Esaki tunnel diodes grown by low temperature molecular beam epitaxy (T_growth=275°C) using in situ boron and phosphorus doping. The effects of ex situ thermal annealing are presented for temperatures between 640 and 800°C. A maximum peak to valley current ratio (PVCR) of 1.47 was obtained at the optimum annealing temperature of 680°C for 1 min. Peak and valley (excess) currents decreased more than two orders of magnitude as annealing temperatures and times were increased with rates empirically determined to have thermal activation energies of 2.2 and 2.4 eV respectively. The decrease in current density is attributed to widening of the tunneling barrier due to the diffusion of phosphorus and boron. A peak current density of 47 kA/cm² (PVCR=1.3) was achieved and is the highest reported current density for a Si-based Esaki diode (grown by either epitaxy or by alloying). The temperature dependence of the current voltage characteristics of a Si Esaki diode in the range from 4.2 to 325 K indicated that both the peak current and the excess current are dominated by quantum mechanical tunneling rather than by recombination. The temperature dependence of the peak and valley currents is due to the band gap dependence of the tunneling probability     

3C-SiC/Si异质结二极管的高温特性

研究了低压化学气相淀积方法制备的n-3C-SiC/p-Si(100)异质结二极管(HJD)在300～480K高温下的电流密度-电压(J-V)特性.室温下HJD的正反向整流比(通常定义为±1V外加偏压下)最高可达1.8×104,在480K时仍存在较小整流特性,整流比减小至3.1.在300K温度下反向击穿电压最高可达220V.电容-电压特性表明该SiC/Si异质结为突变结,内建电势Vbi为0.75V.采用了一个含多个参数的方程式对不同温度下异质结二极管的正向J-V实验曲线进行了很好的拟和与说明,并讨论了电流输运机制.该异质结构可用于制备高质量异质结器件,如宽带隙发射极SiC/Si HBT等.     

Temperature dependence of current–voltage characteristics of MoS2/Si devices prepared by the chemical vapor deposition method

Layers of MoS₂ are directly deposited on the n-type Si (n-Si) substrate by chemical vapor deposition for fabricating a MoS₂/n-Si heterojunction device. The rectification current–voltage (I–V) characteristics of MoS₂/n-Si devices were measured in the temperature range from 80 to 300 K in steps of 20 K. The temperature-dependent forward-bias I–V characteristics can be explained on the basis of the thermionic emission theory by considering the presence of the interfacial inhomogeneous barriers at the MoS₂/n-Si interfaces. The dominance of the induced carrier capture/recombination by states at the MoS₂/n-Si interface that lead to the formation of the inhomogeneous barriers serves to influence the photo-response at room temperature. The fabricated MoS₂/n-Si devices exhibit reversible switching between high and low current densities, when the simulated sunlight is turned on and off. The sensitivity of the I–V characteristics to temperature provides an opportunity to realize stable and reliable rectification behaviors in the MoS₂/n-Si devices. It is found that the electron mobility in the n-Si layer reduces as temperature increases, which leads to the noticeably increased value of the series resistance of MoS₂/n-Si devices.     

Photoinduced transient spectroscopy of defect centers in GaN and SiC

The potentialities of photoinduced transient spectroscopy in terms of investigation of defect centers in wide-band-gap semiconductors are presented. An experimental system dedicated to measurements of the photocurrent transients at temperatures 20–800 K is described and a new approach to extraction of trap parameters from the photocurrent relaxation waveforms recorded in a selected temperature range is presented. The approach is based on the two-dimensional analysis of the waveforms as a function of time and temperature using the correlation procedure. As a result, three-dimensional images showing the temperature changes of the emission rate for detected defect centers are produced and a neural network method is applied to determine the parameters of defect centers. The new approach is exemplified by studies of defect centers in high-resistivity GaN: Mg and semi-insulating 6H-SiC: V. The text was submitted by the authors in English.     

Solution-Processed High-<Emphasis Type="Italic">k</Emphasis> Dielectric,ZrO<Subscript>2</Subscript>, and Integration in Thin-Film Transistors

We report a sol–gel method to deposit a high-k dielectric, zirconium oxide (ZrO₂). This solution-based approach has advantages of easy processing and low fabrication cost. Effects of annealing temperatures on dielectric properties, such as tunneling current density and capacitance density, are reported. Morphological and chemical characterizations suggest that the process temperature can be kept at or below 300°C. We have employed the solution-processed ZrO₂ dielectric in a zinc tin oxide thin-film transistor. Saturation mobility of 4.0 cm²/V s at operating voltage of 2 V has been observed. The measured subthreshold swing is 74 mV/decade, which is the result of the combination of an electronically clean dielectric/semiconductor interface and high insulator capacitance.     

Effect of deep impurity on electric characteristics of epitaxial GaAs structures

The electric characteristics of the p ⁺-i-n ⁺ structures are analyzed for two types of GaAs epitaxial layers: the structures with an i layer based on undoped GaAs and an i layer based on GaAs:Cr. The forward currents of the first-type diodes are caused by recombination in the space-charge region. The reverse I–V characteristics at the voltages to 10–15 V are determined by the component of the generation current. At |U| > 20 V, the current growth is caused by the Poole-Frenkel effect, which is replaced by electron tunneling through the potential-barrier top with increasing the voltage as a result of the electron-phonon interaction. The forward branches of the I–V characteristics of the p ⁺-i-n ⁺ diodes with the i layer based on GaAs:Cr are explained by the unipolar injection in the semiconductor, which is replaced by the bipolar injection with increasing the voltage. The reverse I–V characteristics are linear in the range of 1–15 V; at |U| > 20 V, an increase in current is caused by the impact ionization.     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm