共查询到20条相似文献,搜索用时 62 毫秒
1.
2.
ADSL系统同步技术研究 总被引:1,自引:0,他引:1
实现ADSL收发器系统的一个难点是同步问题,采用DMT调制手段的ADSL收发器系统对同步要求很高,它对同步误差和频率误差要比单载波技术敏感得多,可以说,准确的同步是实现ADSL收发器系统的关键,本对ADSL收发器系统同步技术进行研究。 相似文献
3.
本文介绍了74HC4046的工作原理以及采用74HC4046锁相环芯片组成的图象数字化电路中的行锁相象素时钟(采样时钟)发生器,该发生器的过渡过程快,捕获时间短,跟踪精度高,本文给出了实用电路。 相似文献
4.
本文介绍了单片机控制的高性能时钟同步锁相环的实现方法及性能特点,并简要阐述了其工作原理。在给出该锁相环数字模型的基础上,对锁相环控制软件算法进行分析,在频域给出了2种算法的分析结果,最后给出了主从同步锁相环的硬件测试结果。 相似文献
5.
数字电声系统中最常见也是最不易查找的故障之一,是随机产生的噪声,产生这种噪声的根源往往是时钟系统的问题。本文将试图从“CP噪声”产生的原因开始,讨论如何在系统设计,设备选型,系统安装,参数设定,使用方法等各方面避免与时钟有关的先天缺陷,以保证系统的正常运行。并且给出两个工程实例供读者参考。 相似文献
6.
7.
一种全数字时钟数据恢复电路的设计与实现 总被引:3,自引:4,他引:3
时钟数据恢复(CDR)电路是数据传输系统的重要组成部分.对于突发的数据传输,传统的锁相环法很难达到其快速同步的要求.对此,文中提出一种改进型超前滞后锁相环法的全数字时钟恢复算法,与同类电路比较,具有数据码率捕获范围宽、辅获时间短的优点.文中还介绍了用FPGA来完成该电路设计.理论分析、仿真和实际测试表明,对非归零码,该电路的码率捕获范围5-20 MHz,20 MHz码率时相位抖动容限为2 ns. 相似文献
8.
以数字锁相技术为基础,研制出用于TMR计算系统的容错同步时钟电路。该电路工作稳定、具有完善的容错功能并达到相当高程度的时钟同步水平,在10 ̄30MHz频率范围工作时,4个冗余时钟模块之间的最大相位差都小于5ns,叙述了容错同步时钟电路的工作原理和设计原则,并对引起冗余模块间相位差的各种因素进行了分析。 相似文献
9.
分析了ADSL系统中帧与超帧的结构与性质,由此提出了时域和频域两种帧同步实现方法,介绍了一种简化的搜索帧边界的方案,以及具体的硬件实现,可实现帧边界的快速定位。 相似文献
10.
11.
12.
13.
14.
Effects of clock drift on the performance of a discretetime control system for synchronizing all the clocks in a digital communications network are shown by a detailed analysis of the dynamic behavior of the simple case of a two-node network. With a unidirectional frequency drift of one or both oscillators, it is shown that the buffer stores eventually overflow. A more general linear control scheme is also discussed. 相似文献
15.
The GTD 3 EAX local clock was designed with external synchronization in mind. The initial control algorithms and control circuits required a minimum of change to incorporate the ability to maintain clock synchronization with an external timing reference. The synchronization technique used is a frequency lock method and the considerations necessary for synchronization are described in this paper. 相似文献
16.
本文介绍了广电SDH数字微波电路中时钟同步系统的设计方法;结合河北广电SDH数字微波电路的时钟同步系统方案提出了在实际设计中应该注意的问题,尤其是为避免在时钟主从同步系统中出现时钟环路而应采取的措施。 相似文献
17.
By combining the advanced technologies of a crystal oscillator, LSI, and a computer, an intelligent phase-locked loop (PLL) which uses digital processing (DP) can be created. This kind of PLL, which is referred to here as DP-PLL, includes a microprocessor and a digitally controlled crystal oscillator. It features excellent performance and countermeasures for disturbances of the input signal by stored program control. In this paper, implementation and performance of the DP-PLL are presented with the aim of application in a master-slave network synchronization system. 相似文献
18.
19.
20.
Lam H.K. Wing-Kuen Ling Lu H.H.-C. Ling S.S.H. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):893-903
This paper presents the fuzzy-model-based control approach to synchronize two chaotic systems subject to parameter uncertainties. A fuzzy state-feedback controller using the system state of response chaotic system and the time-delayed system state of drive chaotic system is employed to realize the synchronization. The time delay which complicates the system dynamics makes the analysis difficult. To investigate the system stability and facilitate the design of fuzzy controller, Takagi-Sugeno (T-S) fuzzy models are employed to represent the system dynamics of the chaotic systems. Furthermore, the membership grades of the T-S fuzzy models become uncertain due to the existence of parameter uncertainties which further complicates the system analysis. To ease the stability analysis and produce less conservative analysis result, the membership functions of both T-S fuzzy models and fuzzy controller are considered. Stability conditions are derived using Lyapunov-based approach to aid the design of fuzzy state-feedback controller to synchronize the chaotic systems. Simulation examples are presented to illustrate the merits of the proposed approach. 相似文献