A three-dimensional folded dynamic RAM in beam-recrystallized polysilicon

A three-dimensional folded one-transistor dynamic RAM circuit consisting of an access transistor in a beam-recrystallized polysilicon layer above a storage capacitor has been fabricated. Large cell capacitance and low transistor leakage are obtained by use of multiple polysilicon layers and by folding the storage capacitor beneath the access transistor. The resulting storage times are longer than 1 min, several orders of magnitude greater than storage times in a previously published nonfolded dynamic RAM in recrystallized polysilicon [1].     

A vertically integrated bipolar storage cell in 6H silicon carbidefor nonvolatile memory applications

A vertically integrated one transistor memory cell, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, based on the wide-bandgap semiconductor silicon carbide (SiC), results in a greatly reduced thermal generation rate. Extrapolation of charge recovery data obtained at elevated temperatures suggests a room temperature recovery time of over 10⁶ years     

A dynamic RAM Cell in recrystallized polysilicon

A new, one-transistor, dynamic RAM cell has been fabricated in beam-recrystallized polysilicon. Placing thin oxides both above and below the storage region doubles the storage capacitance. Complete isolation of the storage region by oxides also reduces the susceptibility of the cell to soft errors from collection of charge injected into the substrate by the surrounding elements or by alpha particles. Long storage times are feasible, being limited only by the leakage of the access transistor. A thick oxide under the bit line reduces the bit-line capacitance, further increasing the ratio of storage capacitance to bit-line capacitance.     

An integrated GaAs n-p-n-p thyristor/JFET memory cell exhibitingnondestructive read

An integrated GaAs n-p-n-p thyristor-junction field effect transistor (JFET) structure displays memory by storing charge on the thyristor reverse-biased junctions. The device can be electrically programmed and erased through a single terminal. A buried p-channel, which also functions as the thyristor anode, is used to read stored charge nondestructively over a small range of applied drain voltages (±1.5 V). Measured storage times exceeded 10 s at room temperature with an activation energy of approximately 0.6 eV     

A 10-nW 12-bit accurate analog storage cell with 10-aA leakage

Medium-term analog storage offers a compact, accurate, and low-power method of implementing temporary local memory that can be useful in adaptive circuit applications. The performance of these cells is characterized by the sampling accuracy and voltage droop that can be achieved with a given level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized in a standard 1.5-/spl mu/m CMOS process using an on-chip current integration technique, focusing specifically on the 1 fA to 1 aA current range. These measurements reveal an accumulation-mode source-drain coupling mechanism that can easily dominate diode leakage under certain bias conditions and may have limited previous designs. A simple rule-of-thumb is offered for avoiding this leakage effect, leading to a novel ultra-low leakage switch topology. A differential storage cell incorporating this new switch achieves an average leakage of 10 aA at room temperature, an 8/spl times/ reduction over past designs. The cell loses one bit of voltage accuracy, 700 /spl mu/V on a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min, respectively. This represents a 15/spl times/ increase in hold time at these voltage accuracies over the lowest leakage cell to date, in only 92% of the area. Since the leakage is independent of amplifier bias, the cell can operate on as little as 10 nW of power. Initial measurements also indicate the switch's leakage decreases with the square of process feature size.     

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns     

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C     

Importance of multi-temp testing in automotive qualification and zero defects program

For automotive qualification of Integrated circuits (ICs), multi-temp testing is required by AEC-Q100. In this paper, we demonstrate the importance and necessity of this multi-temp testing in automotive qualification and zero defects program.During the qualification of one of our new products, we found that all samples could pass electrical testing at room temperature after high temperature operating life test, but a few of them failed at hot temperature. One transistor in the circuit was found to have large leakage current. Only at hot temperature, this leakage current was increased (>50 μA) and the fail was detected during hot electrical testing. Root cause was identified and design error is corrected before the release of the product. No failures are observed anymore.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

Extremely low-leakage GaAs P-i-N junctions and memory capacitorsgrown by atomic layer epitaxy

Leakage-limited P-i-N-i-P charge storage capacitors demonstrate a 1/e storage time of over 30 min at room temperature, corresponding to a current density of less than 50 pA/cm² at 1-V reverse bias for a 160×140-μm² capacitor. These storage times are comparable to those of the best MBE-grown structures reported to date. For the diodes tested, which range in size from 4×10^-4 to 4.9×10^-5 cm², leakage is dominated by generation around the etched diode perimeter. The relatively small bulk generation current is evidence of the high quality of the atomic layer epitaxy (ALE)-grown junctions     

High-transconductance p-channel InGaAs/AlGaAs modulation-doped field effect transistors

A p-channel quantum-well InGaAs/AlGaAs modulation-doped field effect transistor has been fabricated. With a 1-µm gate, the device exhibits transconductances of 17.8 and 89 mS/mm at room temperature and 77 K, respectively. Experimental results indicate an extrinsic transconductance greater than 200 mS/mm is achievable with reduced ohmic contact resistance and gate leakage.     

Cryogenic RF switch using III-nitride MOSHFETs

The cryogenic operation of a low-loss RF switch using a AlGaN/GaN metal-oxide semiconductor heterostructure field effect transistor is reported. At 77K the channel resistance of the MOSHFET is three times lower and the contact resistance is 20% lower compared to room temperature. As a result, the performance of the MOSHFET RF switch at 77K is even superior to that at room temperature.     

Multiple-state resonant-tunneling bipolar transistor operating atroom temperature and its application as a frequency multiplier

A resonant-tunneling bipolar transistor with two peaks in the direct as well as in the transfer characteristics is presented. The multiple peaks are obtained by sequentially quenching resonant tunneling through the ground states of a series of double-barrier quantum wells, placed in the emitter of a Ga_0.47In_0.53As-Al_0.48In_0.52 As bipolar transistor, thus obtaining nearly equal peak currents and peak-to-valley ratios. The transistor exhibits current gain of about 70 at room temperature and 200 at 77 K. Peak-to-valley current ratios at room temperature and at 77 K are as high as 4:1 and 20:1, respectively. Frequency multiplication by factors of three and five has been demonstrated using the multiple-peak transfer characteristics of the transistor     

Prediction of data retention time distribution of DRAM by physics-based statistical Simulation

We have developed a comprehensive TCAD framework that can predict the data retention time distribution of a dynamic random access memory (DRAM) chip using the information about the designed cell transistor by coupled physics-based device and statistical simulations. We estimate the cumulative distribution function of the retention time by calculating the leakage currents of a large number of DRAM cells generated by the Monte Carlo methods. The cells have different configurations in the number, locations, and energy levels of the traps that act as localized leakage sources by the extended Shockley-Read-Hall process that includes the trap-assisted tunneling and the stress-induced bandgap narrowing effects. The linear response in the leakage current of each cell to these leakage sources is obtained through the Green's function methods. As an application, we calculate the retention time distribution of a 128-Mb DRAM chip with the 0.18-/spl mu/m ground rule, and verify that the simulation results agree well with the experimental data. We also study the dependence of the retention time distribution on the temperature and negative wordline bias, and discuss the impact of the gate-induced drain leakage on the tail part of the distribution.     

晶体管输出型光电耦合器长期储存寿命研究

介绍了两种长期储存寿命的考核方法,通过对晶体管输出型光电耦合器进行加速寿命试验,记录数据并进行统计分析,利用寿命模型推算出了晶体管输出型光电耦合器常温下的储存寿命。     

A poly-silicon TFT with a sub-5-nm thick channel for low-power gain cell memory in mobile applications

This work presents a gain-cell solution in which a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random-access memory (RAM). This is made possible by the new transistor's 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future.     

Room temperature operation of a quantum-dot flash memory

A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-μA's), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology     

Dynamic sleep transistor and body bias for active leakage power control of microprocessors

In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 /spl mu/s, resulting in 37/spl times/ reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2/spl times/ with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75/spl deg/C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile.     

Novel cell transistor using retractedSi3N4-liner STI for the improvement of dataretention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si₃N₄-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-μm technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si₃N₄-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-μm technology and beyond     

Microwave multiple-state resonant tunneling bipolar transistors

Fabrication and microwave performance of a multiple-state resonant-tunneling bipolar transistor (RTBT) are presented. This transistor exhibits a maximum DC current gain of 60 at room temperature and a cutoff frequency of 24 GHz. Frequency multiplication by a factor of five has been demonstrated with a single transistor