Analysis of Distributed DDQ for QoS Router

In a packet switching network, congestion is unavoidable and affects the quality of real‐time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well‐known solutions for quality‐of‐service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.     

Real-time DSP implementation for MRF-based video motion detection

This paper describes the real time implementation of a simple and robust motion detection algorithm based on Markov random field (MRF) modeling, MRF-based algorithms often require a significant amount of computations. The intrinsic parallel property of MRF modeling has led most of implementations toward parallel machines and neural networks, but none of these approaches offers an efficient solution for real-world (i.e., industrial) applications. Here, an alternative implementation for the problem at hand is presented yielding a complete, efficient and autonomous real-time system for motion detection. This system is based on a hybrid architecture, associating pipeline modules with one asynchronous module to perform the whole process, from video acquisition to moving object masks visualization. A board prototype is presented and a processing rate of 15 images/s is achieved, showing the validity of the approach.     

Modular Cellular Neural Network Structure for Wave‐Computing‐Based Image Processing

This paper introduces the modular cellular neural network (CNN), which is a new CNN structure constructed from nine one‐layer modules with intercellular interactions between different modules. The new network is suitable for implementing many image processing operations. Inputting an image into the modules results in nine outputs. The topographic characteristic of the cell interactions allows the outputs to introduce new properties for image processing tasks. The stability of the system is proven and the performance is evaluated in several image processing applications. Experiment results on texture segmentation show the power of the proposed structure. The performance of the structure in a real edge detection application using the Berkeley dataset BSDS300 is also evaluated.     

一种适用于移动Ad hoc网络的无线P2P应用架构

移动AdHoc网络和P2P技术近年来迅速发展,各种新的应用层出不穷,向广大用户提供了多种新兴服务。相关研究表明,在现有的移动AdHoc网络中直接应用P2P技术,会影响整个网络的性能。本文采用跨层思想,提出新型的无线P2P应用架构,包括了资源搜索和文件传输的整个过程,实现了基于存储内容的分布式网络资源管理。该架构设计了适用于移动AdHoc网络的P2P拓扑结构,定义了各节点内部的模块功能和算法流程。本文还引入用户偏好和信用记录的机制,更好的满足了无线自组织网络中各种P2P应用的不同QoS需求以及每位用户的需求。     

Trinary registers and counters using savart plate and spatial light modulator for optical computation in multivalued logic

Registers and counters are the most important devices in any system of computations. In this paper we have communicated the trinary registers and counters in modified trinary number （MTN） system. It is suitable for the optical computing and other applications in multivalued logic system. Here the savart plate and spatial light modulator （SLM） based optoelectronic circuits have been used to exploit the optical tree architecture （OTA） in optical interconnection network.     

Teaching network connectivity using simulated annealing on amassively parallel processor

A simulated annealing technique for automatically training a machine vision system to recognize and locate complex objects is described. In this method, the training is used to find an optimum connectivity pattern of a fixed number of inputs that have fixed weights, rather than the usual technique of finding the optimum weights for a fixed connectivity. The recognition model uses a two-layer artificial neural network, where the first layer consists of image edge vectors in four directions. Each neuron in the second layer has a fixed number of connections that connect only to those first layer edges that are best for distinguishing the object from a confusing background. Simulated annealing is used to find the best parameters for defining edges in the first layer, as well as the pattern of connections from the first to the second layer. Weights of the connections are either plus or minus one, so that multiplications are avoided, and the system speed is considerably enhanced. In industrial applications on a low-cost parallel SIMD (single instruction multiple data) architecture, objects can be trained by an unskilled user in less than 1 min, and after training, parts can be located in about 100 ms. This method has been found to work very well on integrated circuit patterns     

Classification of multispectral images based on a fuzzy-possibilistic neural network

In this paper, a new Hopfield-model net based on fuzzy possibilistic reasoning is proposed for the classification of multispectral images. The main purpose is to modify the Hopfield network embedded with fuzzy possibilistic C-means (FPCM) method to construct a classification system named fuzzy-possibilistic Hopfield net (FPHN). The classification system is a paradigm for the implementation of fuzzy logic systems in neural network architecture. Instead of one state in a neuron for the conventional Hopfield nets, each neuron occupies 2 states called membership state and typicality state in the proposed FPHN. The proposed network not only solves the noise sensitivity fault of Fuzzy C-means (FCM) but also overcomes the simultaneous clustering problem of possibilistic C-means (PCM) strategy. In addition to the same characteristics as the FPCM algorithm, the simple features of this network are clear potential in optimal problem. The experimental results show that the proposed FPHN can obtain better solutions in the classification of multispectral images.     

Nonlinear adaptive prediction of complex-valued signals by complex-valued PRNN

A complex-valued pipelined recurrent neural network (CPRNN) for nonlinear adaptive prediction of complex nonlinear and nonstationary signals is introduced. This architecture represents an extension of the recently proposed real-valued PRNN of Haykin and Li in 1995. To train the CPRNN, a complex-valued real time recurrent learning (CRTRL) algorithm is first derived for a single recurrent neural network (RNN). This algorithm is shown to be generic and applicable to general signals that have complex domain representations. The CRTRL is then extended to suit the modularity of the CPRNN architecture. Further, to cater to the possibly large dynamics of the input signals, a gradient adaptive amplitude of the nonlinearity within the neurons is introduced to give the adaptive amplitude CRTRL (AACRTRL). A comprehensive analysis of the architecture and associated learning algorithms is undertaken, including the role of the number of nested modules, number of neurons within the modules, and input memory of the CPRNN. Simulations on real-world and synthetic complex data support the proposed architecture and algorithms.     

Single-electron winner-take-all network

A winner-take-all (WTA) single-electron neuron is developed for the first time. This new single-electron circuit is proposed in order to implement a WTA neural network with lateral inhibition architecture. An expression for the neuron's activation function is presented. Furthermore, a dot pattern recognition task is successfully performed by the implemented network considering effects such as offset charges and co-tunnelling.     

Global convergence of Lotka-Volterra recurrent neural networks with delays

Recurrent neural networks of the Lotka-Volterra model have been proven to possess characteristics which are desirable in some neural computations. A clear understanding of the dynamical properties of a recurrent neural network is necessary for efficient applications of the network. This paper studies the global convergence of general Lotka-Volterra recurrent neural networks with variable delays. The contributions of this paper are: 1) sufficient conditions are established for lower positive boundedness of the networks; 2) global exponential stability conditions are obtained for the networks. These conditions are totally independent of the variable delays which are therefore allowed to be uncertain; 3) novel Lyapunov functionals are constructed to establish delays dependent conditions for global asymptotic stability, and 4) simulation results and examples are provided to supplement and illustrate the theoretical contributions presented.     

An analog continuous-time neural network

An analog continuous-time neural network is described. Building blocks which include the capability for on-chip learning and an example network are described and test results are presented. We are using analog nonvolatile CMOS floating-gate memories for storage of the neural weights. The floating-gate memories are programmed by illuminating the entire chip with ultraviolet light. The subthreshold operation of the CMOS transistor in analog VLSI has a very low power dissipation which can be utilized to build larger computational systems, e.g., neural networks. The experimental results show that the floating-gate memories are promising, and that the building blocks are operating as separate units; however, especially the time constants involved in the computations of the continuous-time analog neural network should be studied further.     

通用神经网络硬件中神经元基本数学模型的讨论

在介绍了作者实现通用神经网络硬件中应用的通用计算公式的基础上,提出了一种能同时模拟包括RBF与传统BP网络神经元在内的各种神经元通用的新的数学计算模型,并把基于这种通用数学计算模型的神经网络CASSANDRA-Ⅱ型神经计算机结构设计中并予以硬件实现.文中还讨论了它所模拟神经元网络的灵活性.     

数字电路的最优神经网络模型及建立方法

本文研究电路的最优神经网络模型,获得了对任意结构的多输入多输出逻辑电路,都存在一种最优神经网络能表征电路的逻辑功能,通过求解一个线性方程组可以得到这种神经网络的结构.文中也给出了多输入基本门电路的最优神经网络结构及其能量函数的一般表达式.     

A Pulsed Neural Network With On-Chip Learning and Its Practical Applications

This paper proposes a new model for the pulsed neural network. In this model, the information is coded in terms of firing times of pulses that are generated by the neuron. The pulses transmit through the network and excite the dynamics of the neuron. Their synchronism is utilized to design the architecture of the neural network such that it acts as a radial basis function (RBF) network. A new network-learning algorithm is also developed for this pulsed RBF network. The RBF neurons are generated based on the feature of the training data, and the synaptic delays can be adjusted to distribute these RBF neurons in the training data space. The pulse neural network has been implemented compactly with multiplierless approach for both the forward computation and learning algorithm with a field programmable gate array board. As an application demonstration, it is extended to a nonlinear look-up table and applied to estimate the friction occurs in a precision linear stage     

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.     

Plate-forme pour le déploiement coopératif sensible au contexte

Application deployment in sessions composed of several users is now a hot topic. These users communicate together with heterogeneous terminals. Deployed applications on these nodes must fit to the execution environment and must be interoperable with applications already installed on the others nodes of the session. In this paper, we propose an architecture, which provides a user with missing applications according to the session requirements while respecting compatibility and interoperability constraints. This decentralized and distributed architecture is based on a context-aware deployment algorithm running on each node. After discovering applications scattered on a peer-to-peer network, the algorithm generates deployment configurations needed for any deployment node. Then, the algorithm performs the necessary downloads and instantiations. We present our context-aware deployment platform composed of generic modules. These modules includeApis to build deployment services according to this architecture.     

基于模块电路结构的BP神经网络及其应用研究

本文采用一种简化的BP(Back Propagation)神经网络硬件模块实现方法。该方法利用全电流模式电路组成神经元模块,再用若干模块构成简化的BP神经网络。所提出的模块结构网络系统具有在线学习和在线权值存储能力,且可应用于实现编、解码和二维图像识别。文中提供了PSPICE和高级语言计算机仿真结果。     

ANN based CMOS ASIC design for improved temperature-drift compensation of piezoresistive micro-machined high resolution pressure sensor

The paper investigates the temperature-drift compensation of a high resolution piezoresistive pressure sensor using ANN based on conventional neuron model as also the inverse delayed function model of neuron. Using the delayed neuron model, an improvement in temperature-drift compensation has been obtained compared to the conventional neuron model. The CMOS analog ASIC design of a feed forward neural network using the inverse delayed function model of self connectionless neuron for the precise temperature-drift compensation has been presented. The inverse tan-sigmoid function is realized in CMOS implementation by Gilbert multiplier, differential adder and a cubing circuit. The entire design of the circuit has been done using AMS 0.35 μm CMOS model and simulated using Mentor Graphics ELDO simulator. Using the inverse delayed function model of neuron a mean square error of the order of 10⁻⁷ of the neural network has been obtained against a mean square error of the order of 10⁻³ using conventional neuron model for the same architecture of ANN. This brings down the error from 9% for uncompensated sensor to 0.1% only for compensated sensor using the delayed model of neuron in the temperature range of 0-70 °C. Using conventional neuron based ANN compensation, the error is reduced to 1% error.     

Two-stage neural network architecture for feedback control of dynamic systems

In this paper we investigate system identification and the design of a controller using neural networks. A two-stage neural network design for controllers using single-layer structures with functional enhancements is introduced. This neural network architecture allows the design of a controller with less a priori knowledge about the plant as well as allowing for nonlinear plants. The paper also addresses the special characteristics and problems concerning the use of neural networks in control and demonstrates their performance by showing the successful implementation of a nonlinear control example via simulation.Christop Müller-Dott was a Fulbright Scholar with the Department of Electrical Engineering.     

Circuit Design of On-Chip BP Learning Neural Network with Programmable Neuron Characteristics

A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning.