Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Impact of the vertical SOI `DELTA' structure on planar devicetechnology

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.     

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOl devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Short-channel single-gate SOI MOSFET model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.     

Modes of operation and radiation sensitivity of ultrathin SOItransistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

Generation-recombination noise in the near fully depleted SIMOX SOI n-MOSFET - physical characteristics and modeling

Noise measurement in the linear regime of the device characteristics shows the evolution of an important Lorentzian-like component in the thin-film SIMOX silicon-on-insulator (SOI) n-MOSFET, during the transition from fully depleted to near fully (or partially) depleted operation. The same noise component co-exists with another Lorentzian-like component commonly observed in the kink region, thus distinguishing it from the latter, which is associated with a shot-noise mechanism. Evidence unambiguously shows that local potential fluctuations, caused by random generation-recombination (G-R) processes at bulk defects in the depleted SOI film, are primarily responsible. Extracted trap energy of /spl sim/0.4-0.45 eV below the silicon conduction band edge confirms the involvement of deep-level electron traps, which are probably linked to the residual oxygen and SiO/sub 2/ precipitates in the SOI film. A new analytical G-R noise model yields bulk traps with an average density of /spl sim/10/sup 16/ cm/sup -3/, situated at /spl sim/22-32 nm from the front interface. With an area density comparable to that of the front interface states, the proximity of these bulk traps to the conducting channel in thin-film SIMOX SOI devices accounts for the dominance of bulk-trap induced G-R noise over conventional 1/f noise due to near-interface oxide traps.     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior