一种恒跨导高增益轨到轨运算放大器

基于TSMC 0.18 μm CMOS工艺,设计了一种新颖的恒跨导高增益轨到轨运算放大器。输入级仅由NMOS管差分对构成,采用电平移位及两路复用选择器控制技术,在轨到轨共模输入范围内实现了输入级恒跨导。中间级采用折叠式共源共栅放大器结构,运算放大器能获得高增益。输出级采用前馈型AB类推挽放大器,实现轨到轨全摆幅输出。利用密勒补偿技术进行频率补偿,运算放大器工作稳定。仿真结果表明,在1.8 V电源电压下,该运算放大器的直流开环增益为129.3 dB,单位增益带宽为7.22 MHz,相位裕度为60.1°,整个轨到轨共模输入范围内跨导的变化率为1.44%。     

恒跨导轨对轨CMOS运算放大器的设计

为了提高运算放大器对电源电压的利用率,基于GSMC 0.18 μm CMOS工艺模型,设计了一种高增益恒跨导轨对轨CMOS运算放大器。该运算放大器的输入级采用了互补差分对,并通过3倍电流镜法保证输入级总跨导在整个共模输入范围内恒定;为了获得较大的增益和输出摆幅,中间级采用了折叠式共源共栅结构;输出级采用了AB类输出控制电路,使输出摆幅基本实现了轨对轨。在3.3 V供电电压以及1.6 V输入电压下,该放大器的直流增益为126 dB,单位增益带宽为50 MHz,相位裕度为65°。电路结构简单,易于调试,可大大缩减设计周期和成本。     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

一种低电压恒定跨导轨到轨运算放大器的设计

设计了一种低电压恒定跨导的轨到轨运算放大器,作为误差放大器用在BUCK型DC-DC上实现对输出电压的调节。该运算放大器采用两级结构,输入级采用互补差分对的结构,实现了轨到轨电压的输入,并且利用2倍电流镜技术实现了跨导的恒定;输出级采用AB类放大器的结构,提高了输出电压摆幅和效率,实现了轨到轨电压的输出。该电路基于CSMC 0.25μm EN BCDMOS工艺进行设计,仿真结果表明:电源电压为2.8 V时,在输出端负载电容为160 pF、负载电阻为10 kΩ的情况下,增益为124 dB,单位增益带宽积为5.76 MHz,相位裕度为59.9℃,输入跨导为5.2 mΩ~(-1),共模抑制比为123 dB,输入共模信号范围为0～2.8V,输出电压摆幅为0～2.8 V。     

一种轨对轨CMOS运算放大器的设计

基于0.6μmCMOS工艺,设计了一种轨对轨运算放大器。该运算放大器采用了3.3V单电源供电,其输入共模范围和输出信号摆幅接近于地和电源电压,即所谓输入和输出电压范围轨对轨。该运放的小信号增益为77dB,单位增益带宽为4.32MHz,相位裕度为79°。由于电路简单,工作稳定,输入输出线性动态范围宽,非常适合于SOC芯片内集成。     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

采用输入信号适配技术的BiCMOS运放

为了满足高性能开关电源中集成运放的应用需要,设计了一种结构简单且具有轨对轨输出的运算放大器.该运放基于0.5μm BiCMOS 工艺,采用浮动输出的输入信号适配器(ISAFO),将输入信号放大至差分输入级的工作区域,从而实现了轨对轨的运行.对所设计的运放进行了仿真分析,结果表明在工作电源电压为±0.75 V、外接100 kΩ电阻的条件下,该运放的直流开环增益达到了102 dB,单位增益-带宽为6.35 MHz,相位裕度为62.5°,而功耗仅约为150 μW.所设计的运放具有很宽的共模输入范围及较高的增益,所以特别适用于开关电源的误差放大器、过流、过压和过热保护模块中.     

一种高共模抑制比轨到轨全差分运算放大器

针对传统全差分运算放大器电路存在输入输出摆幅小和共模抑制比低的问题,提出了一种高共模抑制比轨到轨全差分运算放大器电路。电路的输入级采用基于电流补偿技术的互补差分输入对,实现较大的输入信号摆幅;中间级采用折叠式共源共栅结构,获得较大的增益和输出摆幅;输出级采用共模反馈环路控制的A类输出结构,同时对共模反馈环路进行密勒补偿,提高电路的共模抑制比和环路稳定性。提出的全差分运算放大器电路基于中芯国际(SMIC) 0.13μm CMOS工艺设计,结果表明,该电路在3.3 V供电电压下,负载电容为5 pF时,可实现轨到轨的输入输出信号摆幅;当输入共模电平为1.65 V时,直流增益为108.9 dB,相位裕度为77.5°,单位增益带宽为12.71 MHz;共模反馈环路增益为97.7 dB,相位裕度为71.3°;共模抑制比为237.7 dB,电源抑制比为209.6 dB,等效输入参考噪声为37.9 nV/Hz^1/2@100 kHz。     

一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器

设计了一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器.输入级采用PMOS差分对结构,通过电荷泵产生高于电源电压的输入级内电源,使运放在轨到轨输入范围能正常工作并保持输入跨导恒定.电荷泵电路所需的时钟信号通过内部振荡器电路产生,再通过电压自举电路和时序电路产生所需电平的非交叠开关控制信号,最后利用时间交织结构输出连续稳定的高压内电源.在电荷泵实现中还采用了辅助开关结合跟随运放的结构降低了主开关在切换时的毛刺.该运放在折叠式共源共栅结构中使用增益自举结构提高了总体增益,输出级采用class AB类输出结构实现轨到轨输出.该运算放大器基于0.5μm CMOS工艺完成电路与版图设计,仿真结果表明,在5 V电源电压下,直流增益为150.76 dB,单位增益带宽为53.407 MHz,相位裕度为96.1°,输入级跨导在轨到轨输入共模范围内的变化率为0.001 25%.     

A High-Gain, 28GHz, 200kW Gyroklystron Amplifier

A design study of a high efficiency/gain gyroklystron amplifier is performed to demonstrate amplified radiation power of 200kW operating at 28GHz. A key design feature of the present gyroklystron amplifier is that the amplifier is designed to be high gain so that it can be saturated by a low power solid state power amplifier. A non-linear, time-dependent, large signal numerical code is used to predict tube performance. Simulations predict that a stable amplifier radiation power of 214kW is produced with a saturated gain of 54dB, an electronic efficiency of 37%, and a frequency bandwidth of 0.3% from a five-cavity gyroklystron amplifier. The amplifier gain is found to be very sensitive to a beam velocity spread.     

A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques     

A power-efficient, low-distortion variable gain amplifierconsisting of coupled differential pairs

A variable gain amplifier incorporating a plurality of coupled differential pairs has been designed in a bipolar technology. By applying variable offset voltages to these differential pairs, the overall gain of the system can be varied. The linear input region is inversely proportional to gain, making the amplifier very well suited for automatic gain control circuits. Furthermore, the gain of the proposed amplifier is 0-25 dB, the signal bandwidth is 35 MHz, and the output IP3 is 24-30 dBm. It operates from a 5 V power supply and dissipates 40 mW. The active chip area is 0.15 mm² in a 1 μm bipolar technology     

A Single Supply, High Linearity 2-W PA MMIC for WLAN Applications Using Quasi-Enhancement Mode PHEMTs

A fully matched, 2-W high linearity amplifier monolithic microwave integrated circuit, by using quasi-enhancement mode technology of AlGaAs/InGaAs/ GaAs pseudomorphic high electron mobility transistors, is demonstrated for wireless local area network applications. At Vgs= 0 V, V_ds= 5 V, this power amplifier has achieved 14-dB small-signal gain, 33-dBm output power at 1-dB gain compression point, and 34.5-dBm saturated output power with 35% power added efficiency at 5.8 GHz. Moreover, high-linearity with 45.2-dBm third-order intercept point is also achieved     

A 3.1–10.6 GHz Ultra-Wideband Low Noise Amplifier With 13-dB Gain, 3.4-dB Noise Figure, and Consumes Only 12.9 mW of DC Power

A 3.1-10.6 GHz ultra-wideband two-stage pseudomorphit high electron mobility transistor low noise amplifier is presented. The first stage of the amplifier employs a resistive shunt feedback topology and two T-network sections to provide wideband input matching to a 50-Omega antenna. The current-sharing dc bias topology is used to ensure the low power consumption under fixed 3-V battery operation. The amplifier exhibits state of the art performance consuming only 12.9mW of dc power with a power gain of 12.5dB, plusmn0.5dB gain flatness, and 3.4-4.0dB noise figure. Input match is better than -12.0dB, output match is better than -15dB, and group delay is 184pSplusmn28pS     

0.1-42 GHz InP DHBT distributed amplifiers with 35 dB gain and 15 dBm output

An InP double hetero-junction bipolar transistor (DHBT) distributed power amplifier MMIC with 35 dB gain, 42 GHz bandwidth and 15 dBm output power is reported. This represents the highest power and largest gain reported over this bandwidth from a single chip HBT amplifier. A lumped preamplifier with a novel distributed output is used to obtain high gain and wide bandwidth at these power levels.     

MEMSE类放大器

对采用 MEMS开关的 E类放大器进行了原型仿真 ,并且通过工艺流片制作 MEMS开关 ,搭建 E类放大器电路进行测试 .测试结果显示 ,这种机械式的放大器同样能实现有源放大器的功能 .测试得到的放大器实际效率与原型模拟结果一致 ,而放大器的功率增益高达 2 0 0 0 .     

Gallium-nitride microwave Doherty power amplifier with 40 W PEP and 68% PAE

A 40 W gallium-nitride microwave Doherty power amplifier for WCDMA repeater applications is presented. The main amplifier and peaking amplifier are implemented using two 20 W PEP GaN HEMTs. Performance is evaluated for broadband gain, power efficiency and adjacent-channel-power-ratio (ACPR). Experimental results of the GaN Doherty amplifier yielded a power gain of over 11 dB from 1.8 to 2.5 GHz, 68% power added efficiency at 40 W peak power. Good linearity performance of -48 dBc ACPR is obtained at a peak-to-average ratio of 9.8 dB.     

A circuit, waveguide, and spatial power combiner formillimeter-wave amplification

A new concept for a millimeter-wave amplifier that uses circuit, waveguide, and spatial power combining is demonstrated. The passive array has a free-space-to-microstrip insertion loss below -1.5 dB from 30 to 44 GHz. Small-signal measurements of the active array reveal an average gain of 5 dB from 41 to 46 GHz and a maximum gain of 6.4 dB at 45.6 GHz. Large-signal measurements reveal a linear power gain of 2 dB and an output power of 23.7 dBm at the 1-dB compression point at 44 GHz     

Design of transmission optical fiber with a high Raman gain, large effective area, low nonlinearity, and low double Rayleigh backscattering

Designed was the transmission fiber with a high Raman gain, large effective area, low nonlinearity, and low double Rayleigh backscattering (DRBS). Basically the optical signal-to-noise ratio (OSNR) of distributed type Raman amplifier is superior to that of the lumped type Raman amplifier using a high Raman gain fiber such as dispersion compensation fiber. However, much pump power and long length of transmission fiber line are required to acquire a proper gain in the distributed type fiber Raman amplifier. Thus, compositional adjustment on the fiber for optical transmission is of benefit to reduce further the required pump power. In this regard, based on this simulation, the fluorine and germanium co-doped fiber showed a high Raman gain, high OSNR, and low DRBS.