共查询到20条相似文献,搜索用时 218 毫秒
1.
基于布朗运动的分段式电流舵DAC成品率研究 总被引:1,自引:0,他引:1
根据随机过程布朗运动理论,基于分段式电流舵D/A转换器的积分非线性概率密度,建立了积分非线性误差(INL)和D/A转换器分段比的数学模型,获得电流源失配对芯片成品率影响的近似公式,并通过蒙特卡罗方法进行了仿真验证.结果表明,低位采用温度计码编码的D/A转换器成品率较低,而低位采用二进制码编码的D/A转换器成品率较高.当转换位数N<12时,二进制数码越大(>[N/2]),成品率越大;N≥12时,二进制加权码位数不宜过大. 相似文献
2.
3.
12位10MS/sCMOS流水线A/D转换器的设计 总被引:1,自引:0,他引:1
文中介绍了一种六级12位10Msample/s CMOS流水线A/D转换器的设计。该设计方案采用了双差分动态比较器结构,保证了处理模拟信号的精度与速度;采用冗余编码技术,进行数字误差校正,减小了多种误差敏感性,避免了由于余量电压超限而导致的失码,并降低了采样/保持电路和D/A转换电路的设计难度。 相似文献
4.
5.
6.
Wuxi Branch of Southeast University, Wuxi Jiangsu 214028, China; 2.The 58th Institute of China Electronic Technology Company, Wuxi Jiangsu 214035, China
下载免费PDF全文
![点击此处可从《电子器件》网站下载免费的PDF全文](/ch/ext_images/free.gif)
在研究高速D/A转换器的基础上,设计了一种5 V 10 bit高速分段式温度计码D/A转换器.设计的5-1-4温度计译码电路以及对版图布局的优化,使得DAC的DNL和INL最小,该电路的核心由三段式温度计编码控制的47个电流源构成.基于上华0.5μm工艺,采用HSPICE仿真工具对其进行仿真,得到在200 MHz的采样频率下对50 Ω负载满量程输出为45mA,非线性误差为DNL<0.5LSB,INL<0.75LSB. 相似文献
7.
8.
9.
10.
基于"运放共享"电路工作原理,研究了流水线A/D转换器的MDAC模块因采用"运放共享"结构引入的"记忆效应";搭建实际电路,测试出"记忆效应"因子;采用Matlab,仿真了此效应对12位100 MHz流水线A/D转换器各项指标的影响.提出了一种基于FIR数字滤波器的校正算法,在数字域校正模拟电路中由于电容的非理想因素导致的误差.输入为1 MHz正弦波信号时,仿真结果表明,经过数字后台校正后,SFDR为91 dB,SNR为71 dB,流水线A/D转换器系统的指标有了大幅度的提升. 相似文献
11.
A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 n-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 -12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2n-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs 相似文献
12.
13.
Jan-Erik Eklund Christer Svensson 《Analog Integrated Circuits and Signal Processing》2001,26(3):183-190
We present a theory for metastability error power in SuccessiveApproximation A/D converters. The traditional measure, BER, does not accountfor the error influence on signal quality, only the error rate. The metastability error is instead compared with noise, and aSignal-to-Metastability-error-Ratio, SMR, is suggested as a new measure. Suppressing SMR below SNR imposes a gain requirement on the comparator. 相似文献
14.
15.
16.
17.
A 5 bit, 10 Gsample/s flash A/D converter (ADC) is fabricated for 10 Gbit/s optical receivers. To achieve a 10 Gsample/s rate with wide signal bandwidth, the design focuses on reducing aperture uncertainty, clock skew, and metastability error. The ADC achieves 4.1 effective bits at low input frequencies and 2.8 effective bits at 4.9 GHz input signal at 10 Gsample/s. 相似文献
18.
闪耀点(Sparkle)是影响防眩屏幕显示效果的重要因素之一,为满足人们对显示屏分辨率日益提高的要求,闪耀点越来越受到关注。但目前对闪耀点的确切定义,产生原因,表征手段及评价指标等尚无统一的认识和标准。本文从闪耀点现象入手,介绍了目前闪耀点主要的研究表征方法,例如Gollier和Becker各自提出了表征闪耀点的评价测试体系并给出了一系列相关参数;Evans等人在Gollier和Becker工作的基础上进行了一系列心理物理学实验来评价闪耀点现象的实际效果等等。本文就闪耀点的研究现状进行了详尽的综述,为后续屏幕闪耀点研究,建立统一的评价方法与标准提供了宝贵的参考资料。 相似文献
19.
设计了一种能够满足大光斑激光传输的大口径的激光反射镜架,给出满足多维调整使用要求的设计方案,分析了调整架的理论精度、实际精度,分析了误差产生的原因,并根据使用要求对调整架进行了精度设计,进行符合实际的精度分配,使设计满足使用和加工的要求。 相似文献
20.
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on Tm and τ. The flip-flop was fabricated on a 0.25-μm CMOS process 相似文献