A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

Design and modeling of compliant micromechanism for mechanical digital‐to‐analog conversion of displacement

A microelectromechanical digital‐to‐analog converter (MEMDAC) converts digital motion of shuttle actuators operated by the corresponding bits of a binary code into an output displacement proportional to the analog value represented by the input code. In this paper a MEMDAC with improved kinematic design is devised that allows large travel range and high positioning resolution while making the microfabrication process less critical. A lumped‐parameter model of the compliant mechanism of an N‐bit MEMDAC is derived and used to determine the stiffness ratio of flexible members needed for proper mechanical digital‐to‐analog conversion. Furthermore, we analytically investigated the effect of nonuniformity in the device geometry due to the limitations of the microfabrication processes on the linearity of the output displacement. Successful fabrication and release of a 12‐bit MEMDAC demonstrated the manufacturability of the new mechanism, revealing opportunities for MEMS applications in which micropositioners with open‐loop operation, relatively large output range, fine positioning resolution and high repeatability are required. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

FIR and IIR digital filters

A digital filter is a basic building block in any digital signal processing (DSP) system. The simulation results presented show how finite bit precisions can affect the performance of a digital filter. IIR filters are shown to be even more susceptible to finite bit precision effects than FIR filters. However, these effects can be reduced using the IIR filter with a cascaded structure     

A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Implementation of vibration suppression control on FWL processor

In motion or process control systems, a variety of design techniques have been proposed because of the demand for high performance. The higher performance we demand, the higher the degree of the controller becomes. The controller is generally designed by a CAD system and implemented with a microprocessor. But the microprocessor does not have enough precision to realize the results of design by the CAD system. Therefore, the system performance is degraded by finite word length (FWL) effects. To deal with FWL problems, many design methods have been considered in the signal processing field, and high‐ordered digital filters are often used. Among these methods, the implementation technique based on the state‐space realization can minimize the sensitivity to perturbation of coefficients. Noting that optimal realizations with the same transfer function are unique only up to an orthogonal similarity transformation, we must choose the realization within this class of optimal realizations. In this paper, we present an algorithm to find a state‐space realization which minimizes the frequency‐weighted sensitivity measure of the controller performance. Furthermore, we present some experimental results to verify the effectiveness of the proposed algorithm. © 1999 Scripta Technica, Electr Eng Jpn, 128(1): 45–52, 1999     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

高精度相位特性测量系统设计与实现

元器件、模块和接收通道的相位特性(相-频特性、相位-温度特性等)是射频系统设计中需要考虑的一个重要指标;本文提出了一种基于带通采样定理,使用数据采集系统和数字信号处理方法的高精度相位特性测量系统,描述了该系统的设计方案和采用的相位检测方法,通过实际系统测量对系统的性能进行了验证。该系统在宽温度范围内可以测量工作频率在500MHz以下元器件、模块以及输出信号频率低于500MHz的接收通道的相位特性,亦可用于单频信号的高精度相位测量。实际测试结果表明测量分辨力可达到0.025度(RMS)。     

Recent progress on CMOS successive approximation ADCs

Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture, it achieves a very high speed conversion rate of 90 G‐sample/s with an 8‐bit resolution. Also, for applications with very low power consumption, such as wireless sensor nodes, it achieves 84 nW at 10‐bit, 200 k‐sample/s. A high signal to noise and distortion ratio (SNDR) can also be achieved by using several techniques such as an SAR architecture that combines oversampling and noise shaping. This survey paper explains the progress made recently in SAR‐ADC circuit techniques and the achieved performances. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Improvement of high‐voltage impulses in track circuits with Kasami and LS codes

Track circuit systems based on high‐voltage impulses (HVI) have already been used in China to detect the state of track sections. With the demand for more reliable intelligent transportation systems in recent years, new advances, improvements, and innovations are being applied to their development. This work defines a HVI track circuit based on the encoding of the transmitted signal. Not only 15‐bit and 63‐bit Kasami sequences but also 19‐bit and 71‐bit loosely synchronized codes are applied to encode simultaneous HVI transmissions from 2 emitters. Train occupancy in different parts of the track section is also considered. The quality of the detection is evaluated by means of the correlation bounds. Furthermore, a simulation model for double‐track railways has been developed, which can be dedicated to the evaluation of a suitable signal processing in the track circuit under study. Compared to previous HVI track circuits, as a novelty, this work proposes the use of encoded transmissions to these track circuits, to improve their performance in terms of scanned distance and detection accuracy. The correlation properties of the sequences involved also make feasible to avoid any synchronization link between emitters and receivers, thus providing a significant advantage for later deployment.     

Design of a small‐size interlocking system with high availability

An interlocking system consists of an interlocking logical unit and a power controlling unit. After this logical unit calculates the relationship among the train position, the rail shifting position, and the signal, it decides the aspect of the signal. The power controlling unit supplies electrical power to the switch motor and the signal light according to the decision of the logical unit. This paper proposes a small‐sized interlocking system which uses a triplex redundant off‐the‐shelf controller with fail‐safe checker as an interlocking logical unit. A majority voting circuit ensures the safety of parallel output from the interlocking logical unit. This circuit satisfies the condition of total self‐checking (of D.A. Anderson) and also the condition of high availability. In other words, no single fault ever leads to a hazardous state and this circuit ensures safety after single fault occurrence. © 1999 Scripta Technica, Electr Eng Jpn, 128(2): 63–73, 1999     

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

In this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <?61‐dB IMD with 1.25‐GHz sampling frequency.     

一种高分辨率数字时间鉴别器设计

在雷达自动距离跟踪与宽带成像雷达系统中,高分辨率数字时间鉴别器是关键部件,它将跟踪的目标信号相对跟踪波门之间的延迟时间差转换成相应的距离误差。介绍了一种高分辨率数字时间鉴别器的实现过程并给出了仿真结果,为了获得高精度时间分辨率,采用模拟插值技术设计了t/D变换器,代替传统的时钟脉冲计数器对时间延时差的测量,经测试,其测时误差小于200ps,抖动误差小于53ps。     

高精度智能压力传感器的系统设计

本系统CPU采用08051F350,利用其24位A／D转换功能,实现了高精度模拟量数据采集,采用ModBus总线协议与上位机进行通信,将采集到的数据转换成数字信号实时地上传给上位机,并接受来自上位机的数据,进行参数设定。     

基于FPGA的多通道高分辨率时间数字转换系统设计

设计了一种FPGA实现的基于多相位时钟脉冲计数的多通道高分辨率时间数字转换系统。利用多时钟脉冲计数技术,实现数倍于计数时钟频率的计时分辨率,同时实现简便、资源占用少、利于大规模扩展通道数的高精度时间测量需求。尤其适用于阵列光电探测器的激光脉冲飞行时间测量系统。设计实现了64通道、计时分辨率1.25 ns的系统并进行了实验验证。结果表明此系统测量结果标准差优于1 ns,计时分辨率仍有进一步提高的潜力。     

Digital input filters for measurement,control and protection of electric power systems

Power system control and protection equipment has required higher sensitivity and operational reliability than conventional one. Studies of digital signal processing suitable for electric power systems fulfill this objective using fast sampling and digital filtering by a 32-bit floating point DSP (Digital Signal Processor). The sampling rate of 3 kHz is carefully selected in order to separate the power spectrums of the A-D conversion output errors from the signal bandwidth. The new 12-bit A-D conversion unit equipped with a recursive-type digital filter achieved the equivalent high resolution of 14-bit conversion. This paper describes the design concept and the characteristics showing applications to current differential relays, distance relays and power system controllers.     

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R² is 0.99 and verify the effect of duty cycle compensation.     

90dB‐DR 3.3V CMOS single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers for audio applications

This paper presents the design and the realization of single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers to be used in an audio signal processing system. The proposed blocks allow to reduce significantly the pin number of the developed system, while guaranteeing the high quality (16bit) performance required in an audio channel. The proposed circuits have been realized in a standard 3.3V 0.35 µm CMOS technology and achieve a Dynamic Range in excess of 90dB with a Total Harmonic Distortion lower than ‐80dB for a full scale signal amplitude. Their power consumption (≈6mW and each) and the area (0.1mm² each) are finally negligible with respect to the other blocks in the overall systems. Copyright © 2003 John Wiley & Sons, Ltd.     

基于DDS的高精度多路信号发生系统研究

在信号发生器与需要规律信号控制的应用领域中,产生信号的方法通常有2种:一种采用D/A芯片直接输出;另一种采用DDS芯片进行信号输出。2种方式各有利弊,DDS对控制器要求较低,适合于简单或者时变性小的信号发生领域;而D/A芯片则对控制器要求较高,需要控制器一直输出信号,这样就需要一个功能强大的控制器。提出基于ADI公司的AD9850DDS芯片与AVR单片机的信号发生器。系统主要是用于多通道数字开关滤波器等规律信号的场合,因此采用了DDS芯片,同时由于数字开关滤波等应用领域需要多种频率的信号源,系统的最高输出频率125MHz,分辨率达到0.029 1Hz,目前采用DDS的产品中通常的输出频率为100MHz以下,且分辨率仅有1Hz左右,因此本系统性能大大优于同类产品。较使用D/A相比,需要多个高性能控制器,造成成本功耗上升。本系统采用的控制器为Atmel公司的AVR单片,型号为Atmega2560,单片机功耗低,采用单个控制器控制多个DDS的方案,使得系统更加简单,低功耗也更低。整个系统具有较好野外环境适应性以及多用途性,应用前景广泛。