Leakage current mechanisms in SiGe HBTs fabricated using selectiveand nonselective epitaxy

SiGe heterojunction bipolar transistors (HBTs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p⁺ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor. In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe extrinsic base. In these transistors, the Gummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through of the base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakage is shown to be due to a Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole-Frenkel and band to band tunneling. These results are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter     

Si hetero-bipolar transistor with a fluorine-doped SiC emitter anda thin, highly doped epitaxial base

The effect of fluorine doping on SiC/Si heterojunction bipolar transistors (HBTs) is studied. The film properties of the fluorine-doped SiC and device characteristics of an HBT using the SiC emitter and a 50-nm-thick, highly doped epitaxial base (10¹⁹/cm³) are presented. The current gain is improved from 15 to 80 by doping with fluorine. The current gain is four times larger than that of a conventional poly-Si emitter homo-transistor with the same base structure. In spite of the very thin base, the Early voltage is over 100 V. Forward-bias tunneling current was hardly seen at the emitter-base junction. The fluorine appears to terminate the dangling bonds. The results show the possibility of fabricating transistors with a very thin, highly doped base     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

Interfacial oxide, grain size, and hydrogen passivation effects onpolysilicon emitter transistors

The influence of several process variables on the characteristics of polysilicon emitter transistors is studied. The diffusion length of the polysilicon layer was increased using hydrogen passivation, resulting in an increase in the transistor current gain. The increase observed was less than that predicted by the T.H. Ning and R.D. Isaac (1980) transport model, especially at high emitter doping levels. Similarly, the polysilicon grain size had a smaller effect on the current gain than predicted by this model. On the other hand, an increase in the interfacial layer thickness caused a large increase in the emitter efficiency and also resulted in retarded arsenic diffusion and increased emitter resistance and base current ideality factor. The results suggest that reflection of minority carriers at the interface plays a dominant role in determining the emitter Gummel number in devices with heavily doped emitters     

Selfaligned AlGaAs/GaAs HBT grown by MOMBE

The very low parasitic resistance n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBT) grown by metal organic molecular beam epitaxy (MOMBE) using all gaseous source dopants are reported. The carbon and tin dopants were introduced through the uses of trimethygallium (TMGa) and tetraethyltin (TESn). To achieve the low parasitics, the graded InGaAs emitter cap layer was doped with tin to 5*10/sup 19/ cm/sup -3/ and the doping level in the subcollector was 3*10/sup 18/ cm/sup -3/. The emitter and collector sheet resistances were 25 Omega / Square Operator and 10 Omega / Square Operator , respectively. The 800 AA thick base layer was carbon doped to a level of 7*10/sup 19/ cm/sup -3/. The base contact resistance and sheet resistance were 0.1 Omega mm and 180 Omega / Square Operator , respectively. With a thin AlGaAs surface passivation layer for the emitter-base junction, the common emitter DC current gain was maintained up to 25, even for 2*5 mu m/sup 2/ emitter size devices. The unity short circuit current gain cutoff frequency f/sub T/, and maximum oscillation frequency f/sub max/, were 48 and 63 GHz, respectively.<>     

The implementation of a reduced-field profile design forhigh-performance bipolar transistors

The first realization of a reduced-field design concept for advanced bipolar devices using the low-temperature epitaxial (LTE) technique to form the base layer is described. By inserting a lightly doped collector (LDC) spacer layer between the heavily doped base and collector regions, it is successfully demonstrated that the collector-base (CB) junction avalanche multiplication can be reduced substantially while maintaining high collector doping for current density consideration. Similar applications of the LDS technique to the emitter-base (EB) junction also results in a lower electric field, thus less EB junction reverse leakage. The feasibility of the reduced-field profile design concept is demonstrated using a LTE-base device structure     

Inherent and stress-induced leakage in heavily doped siliconjunctions

Inherent leakage currents and leakage induced with reverse-bias stress are investigated in heavily doped emitter-base junctions of polysilicon self-aligned bipolar transistors and similar diodes. Inherent in the devices is a reverse leakage component found to have a perimeter trap-assisted tunneling component characteristic of the Si-SiO ₂ surface and evident at doping insufficient for significant band-to-band tunneling. The band-to-band phonon-assisted tunneling and avalanche leakage components are also identified. Introducing surface states through reverse-bias stress induces a Pool-Frenkel electric field enhanced generation/recombination surface leakage component. The induced and trap-assisted tunneling components are distinct. The induced component is found to saturate as available states, dependent on the peak electric field, are exhausted. Trapped charge accumulation after extensive stressing affects the electric field along the surface reducing the induced and trap-assisted tunneling leakage components     

73-GHz self-aligned SiGe-base bipolar transistors withphosphorus-doped polysilicon emitters

The authors report a thermal-cycle emitter process using phosphorus for the fabrication of self-aligned SiGe-base heterojunction bipolar transistors. The low thermal cycle results in extremely, narrow basewidths and preservation of lightly doped spacers in both the emitter-base and base-collector junctions for improved breakdown. Transistors with 35-nm basewidths were obtained with low emitter-base reverse leakage and a peak cutoff frequency of 73 GHz for an intrinsic base sheet resistance of 16 kΩ/□. Minimum NTL (nonthreshold logic) and ECL (emitter-coupled logic) gate delays of 28 and 34 ps, respectively were obtained with these devices     

Identification of a corner tunneling current component in advancedCMOS-compatible bipolar transistors

A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~10¹⁶ cm^-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×10¹³ cm^-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.     

RTS noise in submicron SiGe epitaxial base bipolar transistors

In this paper, we report a comprehensive study of Random Telegraph Signal (RTS) noise in SiGe epitaxial base bipolar transistors. We analyse the multilevel fluctuations of base and emitter forward currents before and after reverse stress on the emitter-base junction. We show the influence of the chemical treatment preceeding polysilicon emitter deposition on noise properties. We identified that RTS noise arises from different regions in the device : the silicon/polysilicon interface if an oxidizing surface preparation is used, and the emitter periphery after stress-induced degradation. Temperature and bias dependent measurements allowed us to characterize these defects (activation energy, defect type), to analyse their impact to the low frequency noise properties of these transistors and to discuss the role of hot carrier stressing.     

High emitter efficiency in InP/GaInAs HBT's with ultra high basedoping levels

The emitter efficiency of InP/GaInAs heterojunction bipolar transistors is calculated taking into account bandgap narrowing in the base, quantum mechanical tunneling, and the exact doping profile in the base. It is found that the emitter efficiency is high and does not limit the current gain of practical devices, up to a base doping level of 1×10²⁰ cm^-3, and up to 400°K . It is shown that the base emitter junction saturation current can be controlled over two orders of magnitude by a proper small displacement of the doped layer in the base     

Process and device performance of a high-speed double poly-Sibipolar technology using borosenic-poly process with coupling-baseimplant

Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4-μm depth and 1.2-μm width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Ω/square is discussed     

HFE超低温度系数的硅双极晶体管

随着高可靠电子技术的发展，要求硅双极器件的电流增益ＨＦＥ具有很低的正温度系数，发射区重掺杂引起的禁带变窄效应是常规硅双极晶体管ＨＦＥ具有较高正温度系数的主要原因。为了减小这一正温度系数，结合发射区轻掺杂技术，我们采用了新颖的多晶硅部分发射区、多晶硅发射区和非晶硅发射区等结构，获得了电性能优异的ＨＦＥ超低温度系数的硅双极器件，ＨＦＥ的１２５℃高温上升率和－５５℃低温下降率小于２０％，有些甚至小于１０     

Heavy doping effects in p-n-p bipolar transistors

This paper presents the heavy doping effects on the injection current characteristics in p-n-p transistors with a heavily doped but thin base region. The results of the present study indicate that 1) at room temperature the hole current injected into heavily doped base is insensitive to the impurity compensation effect, 2) a linear relationship between the base sheet resistance and the collector-current density is observed when the base doping density is under 1 × 10¹⁹cm^-3. This relationship becomes supralinear as the doping density further increases. As a result, useful current gain exists in thin base transistors even when the base doping is greater than 1 × 10¹⁹cm^-3. From the collector-current-base sheet-resistance relationship and the base doping profile, the effective intrinsic carrier density as a function of the doping density is evaluated and found to increase 8.7 times over that of pure silicon, when the average doping density is 5 × 10¹⁹cm^-3(maximum doping density 1 × 10²⁰cm^-3). 3) The collector current and the current gain of the transistors become less sensitive to the temperature as the base doping density increases. We had observed a current gain up to 30 at 77 K for transistors with the maximum base doping density in the 10¹⁸cm^-3range. The transistors with lower base doping suffer much more degradation in current gain when the temperature is lowered to 77 K.     

Multi-emitter Si/GexSi1-x heterojunctionbipolar transistor with no base contact and enhanced logic functionality

We demonstrate multi-emitter Si/Ge_xSi_1-x n-p-n heterojunction bipolar transistors (HBT's) which require no base contact for transistor operation. The base current is supplied by the additional emitter contact under reverse bias due to the heavy doping of the emitter-base junction. Large-area HBT test structures exhibit good transistor characteristics, with current gain β≈400 regardless of whether the base current is supplied by a test base electrode or one of the emitter contacts. These devices have enhanced logic functionality because of emitter contact symmetry. Since device fabrication does not require base electrode formation, the number of processing steps can be reduced without significant penalty to HBT performance     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

The characteristics of radiation damage under a high or low dose rate in lateral PNP transistors with a heavily or lightly doped emitter is investigated. Experimental results show that as the total dose increases, the base current of transistors would increase and the current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects, especially the double effects of oxide trapped charge, is discussed in heavily or lightly doped transistors. Finally,through comparison between the high- and low-dose-rate response of the collector current in heavily doped lateral PNP transistors, the abnormal effect can be attributed to the annealing of the oxide trapped charge. The response of the collector current, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail.     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

发射区硼掺杂浓度对横向PNP晶体管高低剂量率辐射损伤的影响

本文研究了发射区重硼掺杂和轻硼掺杂横向PNP晶体管的高低剂量率辐照损伤特性。实验结果表明,随总剂量的增加,晶体管基极电流增大,电流增益下降,且轻掺杂PNP晶体管的退化更为严重。文中讨论了辐照感生缺陷在发射区重掺杂和轻掺杂晶体管退化中的作用,特别是氧化物正电荷的双重作用。最后,文章详细论述了高低剂量率辐照下,重掺杂PNP晶体管集电极电流IC的辐照响应。