Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well     

Edge hole direct tunneling leakage in ultrathin gate oxidep-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p⁺ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T_OX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E_OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E_OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected     

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理 ,推导了双栅和环栅 MOSFET短沟效应引起的阈值电压下降 ,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响 ,并用数值模拟验证了理论结果 .这些研究结果对进一步开展纳米 CMOS新器件的研究有很好的参考价值和实际意义     

Analytical model for threshold voltage shift due to impuritypenetration through a thin gate oxide

We derived an analytical model for the threshold voltage shift due to impurity penetration through gate oxide and evaluated the thermal budget for pMOS devices with a thin gate oxide. The threshold voltage shift decreases as the channel doping concentration increases, but the decrease is quite small. The allowable surface concentration of the penetrated impurity increases as the gate oxide thickness decreases if the allowable threshold voltage shift is constant. Therefore, the allowable diffusion length normalized by the gate oxide thickness d_ox increases with decreasing d_ox     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

Investigation of high-performance sub-50 nm junctionless nanowire transistors

The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25 nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25 nm, a 30-40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析ＭＯＳＦＥＴ器件及电路可靠性和进行ＭＯＳＦＥＴ电路设计所必需的．在分析载流子输运的基础上建立了一个常规结构深亚微米ＭＯＳＦＥＴ衬底电流的解析模型,模型公式简单．对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义．     

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

Polysilicon gate enhancement of the random dopant induced thresholdvoltage fluctuations in sub-100 nm MOSFETs with ultrathin gateoxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) “atomistic” simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented     

一种单材料双功函数栅MOSFET解析模型

An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

Understanding the effects of wave function penetration on theinversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1×10²⁰ cm^-3 is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented     

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.     

在薄二氧化硅层上纯多晶硅化镍膜的研究

本文研究了在薄二氧化硅层上快速热退火（RTA）形成的多晶硅化镍膜的电特性，对于在薄二氧化硅上的纯硅化镍膜，测试了其到衬底的泄漏电流，发现二氧化硅性质仍类似于多晶硅膜或纯铝膜下二氧化硅性质，采用准静态C－V方法研究了多晶硅栅和纯硅化镍栅的多晶栅耗尽效应（PDE），并探讨了硅化镍栅掺杂浓度和栅氧化层厚度对PDE的影响，结果表明，即使在未被掺杂的纯硅化镍栅膜，也未曾观察到PDE。     

Impact of extrinsic and intrinsic parameter fluctuations on CMOScircuit performance

The yield of CMOS logic circuits satisfying a specific high performance requirement is demonstrated to be significantly influenced by the magnitude of critical-path delay deviations due to both extrinsic and intrinsic parameter fluctuations. To evaluate the impact of these parameter fluctuations, a static CMOS critical-path delay distribution is calculated from rigorously derived device and circuit models that enable projections for future technology generations. Two possible options are explored to attain a desired yield: (1) reduce performance by operating at a lower clock frequency; and (2) increase the supply voltage and, consequently, power dissipation, to satisfy the nominal critical-path delay. For the 50-nm technology generation, the delay and power dissipation increases are 12%-29% and 22%-6%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration. Combining both extrinsic and intrinsic fluctuations, the delay and power dissipation increase to 18%-32% and 31%-53%, respectively, thus demonstrating the significance of including the random dopant placement effect in future CMOS logic designs     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.