MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.     

A review and projection of semiconductor components for digital storage

Evolution of present integrated-circuit technology over the remainder of the decade should result in semiconductor memories which are competitive with moving-surface memories and other alternatives in many digital storage applications requiring 10⁷-10¹⁰bits capacity. This paper considers MOS, MNOS, CCD, and bipolar component approaches to this objective. Cost, reliability, and power consumption, as affected by technological choices, receive attention. Alternative device technologies and circuit designs are examined. The one-transistor MOS RAM is seen to have potential for considerable growth. Packaging and interconnection methods for low cost and high reliability are considered; evolution of existing techniques is expected. Reliability and maintainability characteristics are seen to be controlled by device technology, component organization, and packaging characteristics. Testing, screening, and error-correction techniques are considered. Projections of component characteristics are extended to outline hypothetical designs for 4-million-bit and 256-million-bit storage systems which might be built by 1980. Features include 64K-bit MOS RAM components on die of area under 100 mm², system selling price of 40 m¢/bit, power consumption well below 1 µW/bit, system MTBF greater than 10⁵h, and physical density on the order of 16000 bits/ cm³. The basis for projected parameters is explained. The advantages and drawbacks of these hypothetical systems relative to moving-surface magnetic storage systems are outlined.     

开关电阻对SC放大器速度的影响和优化方法

在开关电容(SC)放大器中,由于MOS开关导通电阻的存在,会对其建立速度产生影响.首先使用跨导运算放大器的一阶线性模型推导了包含开关导通电阻的开关电容放大器的闭环传输函数,通过分析极点和零点的分布,研究了放大器中不同位置开关的导通电阻对阶跃响应的影响.进而提出了一种MOS开关的优化设计方法来缩短放大器阶跃响应的建立时间.最后使用电路仿真工具验证了该方法的有效性.     

Real-time programmable unit-element SC filter for LPC synthesis

The letter presents a novel programmable unit-element SC filter for LPC synthesis. The circuit is based on the theory of wave-flow networks. It has the advantage that for a programmable 10th-order unit-element SC filter only five programmable capacitor arrays are needed. The capacitive loading of every op amp is constant, thus simplifying the op amp design. The circuit is insensitive to stray capacitances which are commonly associated with integrated MOS capacitors and transistors. It also exhibits a low sensitivity to coefficient quantisations; hence, the circuit is well suited for integration in MOS technology.     

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

CMOS亚阈值特性的低频低压微功耗电路的设计与模拟

工作在亚阈值状态的MOS晶体管具有极小的工作电流和类似于双极型晶体管的指数特性,因此适合于实现微功耗的外部线性内部非线性电流型电路.为了适合于低电源电压的运用,本文给出了一种新型的电流型四象限乘法器以及滤波器,振荡器等基本单元电路,并利用标准0.6-μm CMOS的工艺参数以锁相环为例进行了性能模拟验证.     

Designing the power-handling capabilities of MOS power devices

The considerations involved in the design of soft solder power MOS devices for the industry are described in this study. Numerical models for thermal resistance and thermal fatigue are described with acceptable experimental agreement. An accurate method for the measurement of thermal resistance directly applicable to MOS power devices is described. It has been demonstrated that an optimized die contact geometry will result in rugged MOS devices outperforming, in most cases, their bipolar counterpart.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Electrical measurement of feature sizes in MOS Si2-gate VLSI technology

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very careful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si²-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 µm.     

Electrical Measurement of Feature Sizes in MOS Si/sup 2/-Gate VLSI Technology

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very useful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si/sup 2/-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 //spl mu/m.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

Random error effects in matched MOS capacitors and current sources

Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.     

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.     

Laser scanning for electronic printing

The use of laser scanning techniques for acquisition and printing of images is reviewed with primary emphasis on the printing application. Following an introduction to the basic configuration of laser scanners and to the terminology of this field, some of the principal characteristics of these scanners are summarized. A short overview is given of the key components of scanners, i.e., lasers, modulators, and light deflectors. The integration of these and other components into complete scanning systems is then described, including discussion of optical design issues and several examples of practical optical system design for polygon scanners. Holographic scanners and some of their design considerations are discussed. The electronic and mechanical techniques required for satisfactory scanner design and construction are described. Finally, the embodiment of various design approaches into practical scanners is illustrated by a survey of some existing printer products.     

Low-Voltage MOS Translinear Analog Signal Processing

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them.     

The technological requirements for power by fusion

The major technological requirements for fusion power, as implied by current conceptual designs of fusion power plants, are elucidated and assessed. As the point of departure, the four fusion reactor concepts which have been most thoroughly considered in these design studies are described; they are the mirror, the theta-pinch, the tokamak, and the laser-pellet concepts. The required technology is discussed relative to three principal areas of concern: 1) the power balance, that is, the unique power-handling requirements associated with the production of electrical power by fusion; 2) reactor design, focusing primarly on the requirements imposed by a tritium-based fuel cycle, thermal-hydraulic considerations, and magnet systems; and 3) materials considerations, including surface erosion, radiation effects, materials compatibility, and neutron-induced activation. The major conclusions are summarized in a final section where it is noted that research and development programs have been initiated to satisfy the technological requirements associated with the realization of commercial fusion power.     

Subcarrier multiplexed lightwave system design considerations forsubscriber loop applications

Design considerations for subscriber multiplexed (SCM) systems distributing multichannel analog/digital signals are reviewed. In particular, video distribution schemes based on lightwave transmission technologies are discussed. The two most important system design considerations in an SCM system are the control of intensity noise and nonlinear distortions. Intensity noise characteristics and degradation caused by optical reflections are discussed. Laser and detector linearity requirements are reviewed. System signal-to-noise ratio analysis is performed. Design considerations for receivers for SCM systems are reviewed, and various system applications are examined     

Comparison of coherent optical single-carrier and multi-carrier superchannel with FDM and FDE

Optical superchannel employing single-carrier (SC) and multi-carrier (MC) subband modulation techniques have been widely discussed for high-speed coherent optical transmission and networks. In this paper, we establish uniform system design based on frequency-domain equalization (FDE) and carry out a thorough study on orthogonal frequency division multiplexing (OFDM) superchannel versus SC frequency division multiplexing (SCFDM, also named as DFT-spread-OFDM) superchannel. The baseband signal characteristics of SCFDM and OFDM are analyzed. SCFDM and OFDM superchannel systems with 4-, 16-, 64- and 256-QAM formats and polarization division multiplexing (PDM) are numerically investigated against various impairments. The results show that SCFDM superchannel outperforms its MC counterpart against finite DAC&ADC resolution and fiber nonlinearities, while suffers more penalty when very large dispersion or laser phase noise exists.     

MEMS: the path to large optical crossconnects

Continuous growth in demand for optical network capacity and the sudden maturation of WDM technologies have fueled the development of long-haul optical network systems that transport tens to hundreds of wavelengths per fiber, with each wavelength modulated at 10 Gb/s or more. Micro-electromechanical systems devices are recognized to be the enabling technologies to build the next-generation cost-effective and reliable high-capacity optical crossconnects. While the promises of automatically reconfigurable networks and bit-rate-independent photonic switching are bright, the endeavor to develop a high-port-count MEMS-based OXC involves overcoming challenges in MEMS design and fabrication, optical packaging, and mirror control. Due to the interdependence of many design parameters, manufacturing tolerances, and performance requirements, careful trade-offs must be made in MEMS device design as well as system design. We provide an overview of the market demand, various design trade-offs, and multidisciplinary system considerations for building reliable and manufacturable large MEMS-based OXCs