Reduced-kickback regenerative current comparator for high-speed switched-current pipeline analogue-to-digital converters

A reduced-kickback regenerative current comparator based on a master-slave structure is presented. The master and slave comparators first operate concurrently but, soon, the master's operation is inhibited to prevent the extreme voltage surges, or kickback, from disturbing the driving memory while the slave circuit is allowed to regenerate and produce a valid digital output. Simulations indicate that practically no accuracy degradation in the driving memory cell is detected whereas the same operation using the elementary comparator disturbs the accuracy by more than 4 bits. Designed in a standard 0.35 /spl mu/m 3.3 V digital CMOS technology, the master-slave comparator achieves a sampling speed of 100 MS/s with 7.5 bit resolution, while dissipating 290 /spl mu/W of power from a single 1.8 V supply.     

Novel low-voltage folder for analogue-to-digital converter

A novel architecture of low-voltage folder is presented for folding analogue-to-digital (A/D) converter applications. With MOS transistors completely replacing the resistor load used in the conventional folder, this circuit has a good power-supply–rejection-ratio (PSRR) 21.2?dB for the output common voltage and can work well even under a very low power supply 1.0?V. A moderately high gain 14.5?dB and a wide input bandwidth 506?MHz are obtained. The circuit dissipates only 1.2?mW from 1.2?V power supply. The performance is verified by Hspice-Avanti-99.4 simulations on 0.18?µm digital CMOS technology.     

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

The conventional single-stage comparators, as the basic elements of analogue-to-digital converters (ADCs), are modified for offset and mismatch errors to be utilised in multi-bit per stage pipeline structures. At first, in single-stage comparators, pre-amplification and latch operations are managed by temporary domination of positive or negative feedback via the bulk potential variations in PMOS (p-channel metal oxide semiconductor) devices. Then, the offset correction scheme is added to provide highly matched unit cells within the sub-ADCs of the pipeline structure. Monte-Carlo analysis with 100 iterations shows that input-referred offset reduces to 0.35 mV at σ, while input offset was randomly applied from a Gaussian distribution with 30 mV at 3σ. Using as unit cells of sub-ADCs in a 12-bit 100 MS/s pipeline ADC, ENOB (and SFDR) would be improved from 8.5-bits (and 53.6 dB) to 11.25-bits (and 74.2 dB), when offset error and bulk potential of PMOS devices experiences random variations with 25 mV and 60 mV at 3σ, respectively. Power consumption reaches to 0.45 mW at 625MS/s comparison speed. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology.     

一种用于sub-1V流水线ADC的新型低失调动态比较器

本文提出了一种适用于高速低电压流水线ADC的新型低失调动态比较器。在该比较器中,采用CMOS开关取代了差分对型比较器的两个动态尾电流源。这一改进保持了输入差分对管在比较时刻仍然像差分对型比较器一样工作在饱和区,从而确保该新型比较器拥有像差分对型比较器一样的低失调电压,并能进一步在sub-1V的苛刻条件下也正常工作。而且,它还具有大输入摆幅、低共模敏感度、以及线性的输入输出关系等优点。这种新结构的比较器与两种传统结构的比较器一起在中芯国际0.13微米CMOS工艺下流片验证。对比实测结果验证了此种比较器相对于传统结构的优势。该型比较器也已应用于一款12-bit 100MS/s 的流水线ADC中。     

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS technology.The contrast experimental results verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.     

Logarithmic analogue-digital converter based on a non-linear analogue-to-digital converter

The paper describes a non-linear analogue-to-digital converter (NL-ADC) whose output is proportional to the natural logarithm of the input voltage. It is based on Maclaurin's series of the natural logarithm function. The design is based on voltage-to-frequency conversion (VFC) and a decimal rate multiplier (DRM). The NL-ADC introduces four digital numbers proportional to the first, second, third and fourth powers of the input DC signal. These numbers are digitally added and subtracted according to the first four terms of Maclaurin's series. A microprocessor-controlled hybrid computer with efficient analogue devices is used in the circuit design and implementation.     

30 Gsample/s time-stretch analogue-to-digital converter

High speed analogue-to-digital conversion using a photonic time-stretch preprocessor followed by an electronic digitiser is demonstrated. The preprocessing increases the effective sampling rate and input bandwidth of the digitiser. The system exhibits 30 Gsample/s sampling rate with 26 dB signal-to-noise ratio over a 4 GHz bandwidth     

Enhanced switched-current comparator

Practical techniques for accuracy and speed enhancement in switched-current (SI) comparators are presented. Both techniques require minimum added complexity and, more importantly, possess no performance penalty for the comparator in terms of noise and power. Extensive simulations indicate an enhanced SI comparator with an improvement in resolution of >2.5 bit/s and a speed increase of a factor of 1.35 over those of the basic SI comparator. This makes it feasible for the implementation of an SI comparator with >8.5 bit resolution at an operating speed of >270 MHz for a power consumption of <1.7 mW     

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

As integrated circuit technologies progress to nanoscale, process variations become relatively large and significantly impact circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. In the present scenario, designers are searching for analogue-to-digital converter (ADC) architectures which are nanoscale CMOS processes tolerant. Expectations of the performance of ADCs are continuously increasing along with the progress of digital systems. A process and supply variation tolerant, System-on-Chip (SoC) ready, 1 GS/s, 6-bit flash ADC suitable for integration into nanoscale digital CMOS technologies is presented. The physical design of the ADC has been done using a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit. Baseline post layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC is then subjected to a corner-based methodology of process variation. The results show that process variation causes a maximum variation of 10.5% in the integral non-linearity (INL) and 5.7% in the differential non-linearity (DNL), with both INL and DNL being less than 0.5 LSB. The 90 nm ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators for the ADC have been designed using the threshold inverting technique. To show technology scalability of the design, the ADC has also been presented using a 45 nm Predictive Technology Models (PTM). At 45 nm, INL = 0.46 LSB, DNL = 0.7 LSB and a sampling rate of 100 MS/s were obtained. The 45 nm ADC consumes a peak power of 45.42 μW, and average power of 8.8 μW.     

一种宽输入电压范围软开关电流型DC/DC转换器

针对太阳能光伏及燃料电池等领域电源需要较宽输入电压范围的需求,提出一种通用的具有较宽输入电压范围的软开关电流型DC/DC转换器。该转换器采用了固定频率混合调制设计,可以在所有工作条件下实现半导体器件的软开关工作,并采用电流馈电技术以便适用于低电压高电流的电源。相较于传统转换器,该转换器更为通用,能够实现零电压开关和零电流开关,并且能够在输入电压和负载变化出现较大变化时控制输出电压。实验结果显示,在20-60V输入电压范围内且负载出现变化时,该转换器均表现出良好的性能。     

13 Gsamples/s 5-bit analogue-to-digital converter for coherent optical QPSK receiver

An implementation of an analogue-to-digital converter to be used in a digital coherent QPSK receiver is presented. The converter is manufactured in a SiGe BiCMOS technology and features a resolution of 5 bits with sampling rates >13 Gsamples/s, and dissipates 4.2 W of power.     

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset,and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm × 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.     

Combined radix<2 and 1.5 bit/stage pipelined analogue-to-digital converter

A new pipeline architecture that combines the radix<2 and traditional 1.5 bit gain-stages is presented. The 10 bit, 60 MHz, 3 V pipelined analogue-to-digital converter has been designed in a 0.25 /spl mu/m 1p4M CMOS technology using digital self-calibration. The converter achieves more than 57 dB SNDR from a 3 V supply (10% lower than nominal 3.3 V) within -40 to +120/spl deg/C temperature range.     

一种高精度动态CMOS比较器的设计与研制

比较器的设计对于A／D、D／A转换器的精度至关重要。为满足14位高分辨率A／D转换器的需要，设计了一种高精度动态CMOS比较器，采用二级差分比较和一级动态正反馈latch结构实现了高比较精度。预增益和Latch级的应用降低了功耗。设计中充分考虑了工艺离散性和使用环境温度与电源变化的影响，保证了成品率和电路在变化工作环境下性能指标的实现。仿真结果表明，设计的高速动态比较器LSB（Least Significant Bit）为±0．15mV，输入动态范围为VSS-VDD（VSS为地电压，VDD为电源电压），相应于14位比较精度。功耗6．28mW，工作频率3．6MHz。电路用0．6μm双层金属、双层多晶硅CMOS工艺实现。     

Enhanced linear dynamic range property of Franz-Keldysh effectwaveguide modulator

The spurious-free dynamic range (SFDR) of an InGaAsP-InP Franz-Keldysh effect (FKE) waveguide modulator is studied. Low-biasing the FKE modulator is shown to enhance the SFDR by 22 dB with a 3-dB optical power penalty. Polarization-independent RF operation is also obtained with low bias. At 2 mA photocurrent, the simulated narrowband and broadband SFDR are, respectively, 127 dB and 104 dB in a 1-Hz bandwidth. The measured result projects a narrowband SFDR of 129 dB-Hz ^4/5 at this photocurrent     

A low propagation delay dispersion comparator for a level-crossing AD converter

This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.     

A novel comparator featured with input data characteristic

Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators.     

A 2-D GRO Vernier time-to-digital converter with large input range and small latency

The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X-axis phases and Y-axis phases (based on 2-D definition) can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90 nm CMOS process and consumes 1.8 mA from 1.2 V. The measured input range can safely cover a full period of a 50 MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.     

A new high-speed periodic-threshold comparator for use in aJosephson A/D converter

A Josephson comparator based on a nonhysteric one-junction superconducting quantum interference device (SQUID) for use in a periodic-threshold A/D (analog-to-digital) converter is discussed. Simulations show that a 4-bit A/D converter using this comparator could have a sampling rate of >20 GHz with an analog signal bandwidth of >10 GHz. This performance represents a factor-of-greater-than-five improvement over that of other periodic-threshold A/D converters, which are based on two- or three-junction SQUIDs