MPEG-4中DCT算法的研究及实现

在MPEG-4电路中，DCT是整个算法中运算量最大的一部分。为了使性能达到最优，本文运用种新的算法思想将二维DCT分解成两次一维变换的过程，一次为行变换，一次为列变换。经过分解后的DCT算法得以简化，更适合于硬件实现。在设计使用的Verilog语言和仿真由Modelsim来完成并给出硬件电路实现结构。     

计算q1^l×q2^l二维DCT的快速算法

离散余弦变换(DCT)广泛应用于信号处理的许多领域,多维DCT(MD-DCT)是图像处理和视频信号处理的重要工具.通常,多维DCT采用行列法用一维算法实现,实现效率较低.近年来虽然出现了一些多维DCT直接实现算法,但大多要求变换为2n×2n,限制了适用范围.该文研究较一般的二维DCT快速算法,将ql1×ql2(q为奇素数;l1,l2分别为两个不同的整数)二维DCT转化为多项式变换和一维简化余弦变换,通过特别设计的快速多项式变换算法和1D-RDCT递归分解算法,提出了一种计算复杂性较低且具有规则运算结构的ql1×ql2二维DCT算法.本算法的设计方法可以方便地推广到多维(>2)的情况.     

计算q~(l_1)×q~(l_2)二维DCT的快速算法

离散余弦变换 (DCT)广泛应用于信号处理的许多领域 ,多维 DCT(MD- DCT)是图像处理和视频信号处理的重要工具 .通常 ,多维 DCT采用行列法用一维算法实现 ,实现效率较低 .近年来虽然出现了一些多维 DCT直接实现算法 ,但大多要求变换为 2 n× 2 n,限制了适用范围 .该文研究较一般的二维 DCT快速算法 ,将 ql1 × ql2 (q为奇素数 ;l1 ,l2 分别为两个不同的整数 )二维 DCT转化为多项式变换和一维简化余弦变换 ,通过特别设计的快速多项式变换算法和 1D- RDCT递归分解算法 ,提出了一种计算复杂性较低且具有规则运算结构的 ql1 × ql2 二维 DCT算法 .本算法的设计方法可以方便地推广到多维 (>2 )的情况 .     

AVS标准中整数DCT变换快速算法的硬件设计

介绍了AVS标准中整数DCT变换矩阵的化简方法,该方法提高了一维整数DCT变换硬件实现的速度。基于此一维整数DCT变换,采用模块复用和流水线设计,实现了二维整数DCT直接变换在一个时钟周期内完成,工作频率可达160MHz。仿真结果证实了该算法的有效性。     

基于多项式变换的二维整型离散余弦变换快速算法

提出了一种基于多项式变换的二维整型离散余弦变换（DCT）快速算法,利用多项式变换将二维DCT变换的计算转化为一系列一维DCT变换及其变换系数的求和运算,减少了乘法和加法的计算量;利用提升矩阵,实现了整型DCT变换,进一步提高了运算效率的同时,使信号可精确重构。     

一维图像识别实现虚拟触摸屏系统

为避免大屏幕触摸屏中人体遮挡无法识别手指的问题设计了一种虚拟触摸屏系统,由至少两个一维图像采集装置、显示屏和数据处理装置构成。一维图像采集装置可以是一维线性传感器,配合镜头、信号转换和接口电路实现;也可以是市场上易于购得的二维图像采集装置摄像头,使用其一维图像数据。由一维图像采集装置采集手指在虚拟触摸屏上的一维图像数据,根据多个一维坐标点位置与二维虚拟触摸屏上点位置的一一对应关系,由数据处理装置将其转换为手指触摸屏幕上的二维直角坐标,从而完成对应的操作,实现人机交互。     

高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

PDF417条码及其识读

详细介绍了 PDF4 17二维条码的符号结构 ,并以此为基础设计了译码器的硬件电路和相应的译码软件 ,从而识读 PDF4 17二维条码及大部分一维条码 ,具有很好的应用价值     

适用于嵌入式系统的二维DCT算法

提出一种简单、快速的二维DCT算法,即将二维DCT的变换系数和图像的像素值事先 乘好,形成查找表,在实现直接二维DCT变换时,把表调入内存,乘积的结果就能通过寻址的方式得 到而无需乘法器,速度很快,非常适合嵌入式系统的设计。在设计查找表时,优化了其结构,减小了存 储空间。实验结果表明了算法的有效性。     

矢量基二维离散余弦变换

本文提出一种频率抽取(DIF)矢量基二维离散余弦变换(2D DCT)快速算法。该算法将H.S.HOU的一维离散余弦变换(ID DCT)递归快速算法推广到二维,利用三角恒等式cos(α+β)=2cosαcosβ—cos(α—β),得出数值稳定的二维离散余弦变换快速矢量基算法。其数值稳定性比Haque提出的矢量基2D DCT算法要好,和常用的行列算法相比节省25%乘法运算量。文中给出了算法流图。     

3-D VLSI technology in Japan and an example: a syndrome decoder for double error correction

This paper consists of two parts. The first part is a survey of Three-Dimensional (3-D) VLSI technology which is considered to be one of the leading areas among the integrated circuit technologies in the next century. Furthermore the researches of 3-D VLSI in Japan are summarized as well.In the second part of this paper, as a case study, the features of 3-D VLSI are exhibited by testing various layouts of syndrome decoder for double-error correction of linear codes, which can be used for example to improve the reliability of main memories. By the layout results of DEC-BCH decoder, material as well as time savings using 3-D VLSI technology compared to the conventional 2-D VLSI technology are shown.     

基于DA算法的二维离散余弦逆变换的ASIC设计

离散余弦变换已成为图像压缩中一标准技术，本文给出了基于DA的二维离散余弦逆变换（2－DIDCT）的ASIC设计。本设计通过采用快速1－DIDCT算法及基于DA算法的乘法累加器来减少面积、加快速度。设计采用自顶向下设计方法，用VHDL进行描述，整个系统在SYNOPSYS工具上进行设计及仿真，最终综合到门级电路。     

基于FPGA的二维码图像旋转系统

阐述了在图像预处理阶段将二维码图像旋转至端正的必要性。设计了一种求取QR二维码图像旋转角度的算法以及一种可将二维码图像旋转任意角度的算法。求取旋转角度算法简捷有效,能以较低的硬件代价实现。图像旋转算法利用了CORDIC算法以及双线性插值算法,采用高速流水线架构在FPGA上实现。整个设计在Altera公司的DE2平台下进行了验证。实验结果表明,这两种算法结合使用可以快速有效地将带有一定歪斜角度的二维码图像旋转端正,速度可以达到90.9 MHz,旋转后的图像细节清晰,能有效提高二维码的识别率。     

基于FPGA的二维DCT IP核优化设计

采用行列分解法实现了二维DCT变换,其一维DCT采用Loeffler算法结构,结合位宽优化与CSD乘法优化,在FPGA芯片上无内嵌硬件乘法器情况下,一维DCT计算模块仅需要1504LUTs;有内嵌硬件乘法器情况下,仅需要688LUTs与22个内嵌9*9乘法器。将二维DCT计算模块封装为wishbone接口的IP核,在AlteraDE2-70开发板上实测二维DCT计算速度是软件快速DCT算法的296倍,可应用于JPEG图像处理、音频处理等场合。     

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

Two-dimensional discrete cosine transform on sliding windows

The discrete cosine transform (DCT) has been successfully used for a wide range of applications in digital signal processing. While there are efficient algorithms for implementing the DCT, its use becomes difficult in the sliding transform scenario where the transform window is shifted one sample at a time and the transform process is repeated. In this paper, a new two-dimensional sliding DCT (2-D SDCT) algorithm is proposed for fast implementation of the DCT on 2-D sliding windows. In the proposed algorithm, the DCT coefficients of the shifted window are computed by exploiting the recursive relationship between 2-D DCT outputs of three successive windows. The theoretical analysis shows that the computational requirement of the proposed 2-D SDCT algorithm is the lowest among existing 2-D DCT algorithms. Moreover, the proposed algorithm enables independent updating of each DCT coefficient.     

基于SS序列集成电路布线技术

集成电路(IC)是在半导体基片上形成的完整的电子线路。当前芯片里的电路与系统日趋复杂,超大规模集成电路(VLSI)设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。本文重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平/垂直约束图提取版图中各单元的坐标。并根据要连模块的位置关系对其连线经过的模块进行有条件加线宽的处理。     

Research in Design Automation for VLSI Layout

Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the design of custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA tools in both master-slice LSI circuit design, and the custom design of VLSI circuits with up to 100,000 gates. Algorithms for VLSI DA systems include automatic floor planning, automatic cell placement, and automatic routing. Hierarchical design is an efficient approach to the layour of huge numbers of transistors; a VLSI circuit with 74,000 transistors and 17,000 gates was designed using such an approach. The layout design effort required less than 10 man-months, and the chip was fabricated with no error on the first design.