Channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories

The channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories is investigated. While the trapped charge profile-dependent overerasure is observed in 10-μm-wide device, it is suppressed in 0.22-μm-wide device. Both the overerasure suppression and gradual positive threshold voltage shift in narrow device are explained as an elevated hot hole injection efficiency followed by more pronounced redistribution of the hole profile in the channel-center and the suppression of the lateral migration of injected holes in the channel-edge, by combining the measured endurance characteristics and TCAD simulation results. Main physical mechanisms are three-dimensional distribution of the electric field by gate/drain voltage, increasing interface states, and their trapped charge with cycling in the channel-edge.     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

Characteristics of interface-doped MNOS memory devices

The results of an investigation of the characteristics of MNOS memory devices are given in which the interface between the oxide and nitride was doped with a few monolayers of various refractory metals. In particular, write speeds of the order of microseconds could be obtained along with retention times which could be extrapolated to many decades. No temperature dependence could be found for the decay of stored charge between 77 K and 300°C, indicating that retention is normally dominated by Fowler-Nordheim back tunneling from the interface. Long time exposure to high gate voltages and write/erase cycling in excess of 1000 cycles sharply reduces the achievable memory window, and is accompanied by the copious generation of fast surface states, at least in p-channel devices.     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Charge transfer properties of mnos structures as influenced by processing parameters

The charge transfer and retention characteristics of MNOS structures have been studied as a function of specified processing parameters utilized when fabricating the tunneling silicon oxide and charge storage silicon nitride layers. A grid array of n₊ junctions fabricated on 2 ohm-cm “p” type silicon substrates allowed simulation of the transient characteristics of FET’s. Electrical measurements included switching speed, static and dynamic charge storage windows, and stored charge retention with time. The switching speed and window width were influenced by some processing parameters. Some shortcomings with recent discharge models are noted, based upon the data obtained. Limited (multiple cycling) “fatigue” studies have indicated improved window behavior with increased write-erase voltages, and pulse widths below one microsecond, for MNOS structures with the tunneling oxide prepared within an NO plus H₂ ambient.     

Electrons retention model for localized charge inoxide-nitride-oxide (ONO) dielectric

An electrons retention model for localized charge, trapped in ONO stacked dielectric, is introduced utilizing the nitride read-only memory (NROM) device. The observed reduction in threshold voltage (retention loss) of a programmed cell is explained in terms of lateral charge redistribution in the nitride layer. Assuming a thermal emission mechanism, the energy levels of the electrons traps were extracted and found to be distributed continuously in the nitride band gap, with a median value of ~2.12 eV below the conduction band. Utilizing these findings, the model allows a prediction of the retention loss over wide range of temperatures, between 140°C-300°C, long times, up to 10 ⁷ s, large retention loss levels, ~90%, and programming windows, 1.9-3.3 V. Based on this work the ten-year relative retention loss at 140°C of an NROM cell is expected to be 14% (V_DS=0.1 V) and the equivalent uncycled product loss is expected to be 8%     

Memory traps in MNOS diodes measured by thermally stimulated current

Thermally stimulated current was measured to determine trap distribution and charging and discharging mechanisms in a Metal-Nitride-Oxide-Semiconductor (MNOS) diode with 16 Å oxide thickness. By changing gate voltage, heating rate and the initial flat-band voltage, the memory traps near the nitride-oxide interface were separated from the others. The general formula was derived for the thermally stimulated current in an MNOS diode and was applied to obtain the trap distribution as well as effective emission time constants. The results indicate that the memory traps are distributed 50 Å deep into the nitride film from the nitride-oxide interface. The energy level lies at around 2·55 eV from the bottom of the nitride conduction band. The charging and discharging mechanism is the cascade connection of tunneling and thermal excitation or trapping. The obtained trap distribution and the charge transfer mechanism are successful for interpreting the write-in and retention characteristics.     

Evidence of hole flow in silicon nitride for positive gate voltage

This paper discusses the conduction mechanism of silicon nitride. n-channel transistors and MOS capacitors with the top-oxide/ nitride/bottom-oxide dielectric structure were used to characterize the dielectric conduction. Top and bottom oxides were found to have different effects on the dielectric leakage current and electron and hole tunneling. This implies that the dominant charge carriers across the top and bottom oxides are different. We claim the conduction through a bottom oxide is dominated by electron flow and conduction through a top oxide and the nitride is dominated by hole flow for positive gate voltage. Energy band diagrams are presented to discuss the effective trap level for hole conduction in the nitride and holes and electrons tunneling through the oxide/nitride/oxide dielectrics.     

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.     

Physical understanding and modeling of SANOS retention in programmed state

SANOS technology is the first time accurately analyzed and modeled. Firstly, the retention is studied on capacitors to determine the main retention mechanisms. The electron detrapping in the silicon nitride, followed by tunneling through the aluminum oxide is found to be the dominant mechanism causing the retention loss. The modeling of this effect reproduces the observed temperature, gate work function and window dependency. Secondly, these results are applied to scaled devices where the retention is dominated by the same mechanisms. The difference in the retention loss between capacitors and devices is explained by a different field distribution in the gate dielectric. Thirdly, the issue of lateral redistribution occurring at high temperature in scaled transistors is analyzed by 2D simulations and retention tests in SONOS devices.     

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.     

High-temperature charge loss mechanism in a floating-gate EPROMwith an oxide-nitride-oxide (ONO) interpoly stacked dielectric

The intrinsic charge loss rate of a floating-gate EPROM cell at temperatures above 300°C appears to be much higher than the prediction from the authors' previous model (1990) developed at lower temperatures. A detailed study of intrinsic charge loss rate at temperatures ranging from 340 to 430°C reveals that it follows a Frenkel-Poole model with a barrier height of 1.9 eV. The physical origin of this high-temperature charge loss is proposed. The model suggests that electrons leak through the thin bottom poly oxide and nitride, and then thermally surmount the barrier at the nitride/top-oxide interface     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.     

Pulse-$IV$ Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide

The transient behavior of SONOS-type devices was investigated for the first time using pulse- $IV$ technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC–$IV$ method. By using specific pulse-$IV$ setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 $muhbox{s}$ at low gate voltages ($≪$ 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.      

Threshold voltage instability of nanoscale charge trapping non-volatile memory at steady phase

Post program/erase (P/E) cycled threshold voltage (Vt) instability is one of the major reliability concerns for nanoscale charge trapping (CT) non-volatile memory (NVM) devices. In this study, anomalous program state Vt instability of fully annealed nanoscale nitride based CT NVM device at steady phase is carefully examined. To the best knowledge of the authors, for the first time, the relationship between the derived apparent activation energy (Eaa) of this anomalous program state Vt instability at steady phase and the P/E cycle count is established. They are found to adhere to the power law decay relationship. Anomalous program state Vt instability at steady phase was found to favor lateral redistribution of trapped charge model instead of vertical charge transport model. Physical interpretations of its underlying physical mechanisms and reliability implications to reliability performance of nanoscale nitride based CT NVM were presented. Plausible technical solutions to mitigate the reliability degradation induced by this anomalous program state Vt instability on nanoscale nitride based CT NVM were proposed.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).     

Endurance and retention of mnos devices over the temperature range from −50°c to +125°c

The effect of temperature variation on the endurance and retention characteristics of MNOS devices has been studied over the temperature range from −50°c to +125°C. The endurance of MNOS devices is significantly degraded as temperature is increased. Retention, on the other hand, appears to be a more sensitive function of endurance cycling than increased temperature. Increased nitride conductivity, thermal excitation tunneling and charge centroid movement at higher temperatures along with increased surface state density caused by endurance cycling are suggested as mechanisms to explain observed degradation in device performance. This work was supported by Sandia National Laboratories Contract #46-2392 Now at: Division 2144, Sandia National Laboratories, Albuquerque, New Mexico 87115     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Experimental study of carrier transport in multi-layered structures

Gate stress measurements are applied to Flash cell array structures. The counter intuitive V_t shift is associated to the charge redistribution in the ONO layer. This redistribution of charge follows Poole–Frenkel conduction mechanisms. In multi-level Flash, the total charge in the nitride layer need to be minimized, and well-controlled, in order to achieve good data retention of the device.     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps