A comprehensive model of PMOS NBTI degradation

Negative bias temperature instability has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the reaction–diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work. We also augment this basic reaction–diffusion model by including the temperature and field-dependence of the NBTI phenomena so that reliability projections can be made under arbitrary circuit operating conditions.     

A comprehensive model for PMOS NBTI degradation: Recent progress

Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.     

A comprehensive delay model for CMOS inverters

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE     

A degradation model for metallized polyester capacitors

Till now it was usual to think that the physical degradation of the end-spray contacts of metallized polyester capacitors, accelerated by exposure to high temperature, only implied an increase of the equivalent series resistance. This paper reports that together with this resistance increase, a contribution due to a parasitic capacitance must be taken into account to describe this degradation mechanism correctly.A degradation model is presented that enables fairly good fitting of experimental measurements of capacitance, dissipation factor and impedance vs. frequency of capacitors submitted to long-term tests, that exhibit an electrical behaviour deviating from the one described by the usual equivalent series circuit.The paper illustrates a technological analysis method that enables the consistence of the proposed model to be confirmed and that can currently be used to make quick estimations of the reliability performance of components by different manufacturers and to carry out periodic quality control.It was also seen that, in well manufactured capacitors, the described degradation mechanism is rather slow, with respect to the high temperature exposure time, so that the reliability level of these components is not affected.     

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 10¹²eV^-1. cm^-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.     

A comprehensive model for photomixing in ultrafast photoconductors

A comprehensive model for photomixing phenomenon in a dc-biased ultrafast photoconductor is proposed. The dependence of the carrier lifetime and carrier velocity on the electric field is taken into account, and the significance of carrier transport and carrier generation and recombination mechanisms in a terahertz photomixer are evaluated. A method for calculating the nonuniform induced electric field due to excess charge density resulting from unequal electron and hole recombination lifetimes is presented.     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

A comprehensive model for the modal dynamics of vertical-cavitysurface-emitting lasers

We present a quasi-3-D dynamic model of vertical-cavity surface-emitting lasers (VCSELs). The interdependent processes of carrier transport, heat generation and dissipation, and optical fields are solved self-consistently for each point in time and space. An effective index model is adopted for the evaluation of the optical fields in the complex layer structure. The inclusion of a temperature- and carrier-density-dependent refractive index, and its time dependence, allows us to study the evolution of the transverse optical field distributions under dynamic conditions. The model is applied to a typical index-guided structure with a 7-μm oxide aperture. A direct comparison is made using "cold" cavity modes, which is a normal technique when modeling the dynamics of VCSELs. Significant discrepancies are demonstrated both at smalland large-signal modulation, which indicates the need of a more sophisticated model for accurately predicting and understanding the geometry-dependent modal evolution     

A comprehensive analytical model for metal-insulator-semiconductor(MIS) devices

A comprehensive model for metal-insulator-semiconductor (MIS) devices under dark conditions which consists of a wide range of parameters has been developed. Parameters neglected by other authors have been included. The effects of surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function are taken into account. The permittivity and barrier height of thin oxide are included in the calculation. The limits on equilibrium and nonequilibrium are explored     

A comprehensive circuit-level model of vertical-cavitysurface-emitting lasers

The increasing interest in vertical-cavity surface-emitting lasers (VCSEL's) requires the corresponding development of circuit-level VCSEL models for use in the design and simulation of optoelectronic applications. Unfortunately, existing models lack either the computational efficiency or the comprehensiveness warranted by circuit-level simulation. Thus, in this paper we present a comprehensive circuit-level model that accounts for the thermal and spatial dependence of a VCSEL's behavior. The model is based on multimode rate equations and empirical expressions for the thermal dependence of the active-layer gain and carrier leakage, thereby facilitating the simulation of VCSEL's in the context of an optoelectronic system. To confirm that our model is valid, we present sample simulations that demonstrate its ability to replicate typical dc, small-signal, and transient operation, including temperature-dependent light-current (LI) curves and modulation responses, multimode behavior, and diffusive turn-off transients. Furthermore, we verify our model against experimental data from four devices reported in the literature. As the results will show, we obtained excellent agreement between simulation and experiment     

A biased percolation model for the analysis of electronic-device degradation

The biased percolation model is proposed for investigating device degradation and failure associated with the generation of defects due to local Joule heating. The degradation processes of a thin conducting or semiconducting film is monitored by a set of relevant indicators, such as: the evolution of damage pattern, the current distribution, the film resistance and its fluctuations, the defect concentration, the film lifetime, etc. The conductor-insulator (CI) and conductor-superconductor (CS) like degradation processes are considered. The results can be used to propose non-destructive indicators to test the reliability of samples and to interpret the corresponding experiments.     

A mobility model for submicrometer MOSFET simulations includinghot-carrier-induced device degradation

The model presented includes the quantum effects of electrons in the inversion layer proposed by S.A. Schwarz and S.E. Russek (1983) and the surface scattering effects due to the interfacial charges. By comparison with experimental data from scaled MOSFETs, the limitation of K. Yamaguchi's (1983) mobility model in submicrometer device simulations is implied, while the quantum channel broadening effects have been proven significant in turn. In addition, it is shown that the modeling of the screening effect of Coulomb scattering plays an important role in simulating the hot-carrier-induced MOSFET degradation. The model can predict the current-voltage characteristics within 5% accuracy for scaled MOSFETs down to 0.5-μm, as well as the degradation of electrical characteristics due to hot-carrier effects for submicrometer MOSFETs     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation

The hot-carrier degradation of lightly doped drain nMOSFETs is studied in detail. The degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The degradation behaviour of a characteristic MOSFET parameter is modelled over the complete degradation range, from 0.02 up to more than 10%. Furthermore, the introduction of a simultaneous non-linear least-square fit of the degradation curves has been successful for predicting the complete degradation behaviour at normal operating conditions.     

A physical-based analytical model for hot-carrier inducedsaturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits     

A bidirectional NMOSFET current reduction model for simulation ofhot-carrier-induced circuit degradation

An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, ΔI_D is implemented as an asymmetrical voltage-controlled current source and the new ΔI_D model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented     

A Wiener process model for accelerated degradation analysis considering measurement errors

Accelerated degradation analysis plays an important role in assessing reliability and making maintenance schedule for highly reliable products with long lifetime. In practical engineering, degradation data, especially measured under accelerated condition, are often compounded and contaminated by measurement errors, which makes the analysis more challenging. Therefore, a Wiener process model simultaneously incorporating temporal variability, individual variation and measurement errors is proposed to analyze the accelerated degradation test (ADT). The explicit forms of the probability distribution function (PDF) and the cumulative distribution function (CDF) are derived based on the concept of first hitting time (FHT). Then, combining with the acceleration models, the maximum likelihood estimations (MLE) of the model parameters are obtained. Finally, a comprehensive simulation study involving two examples and a practical application are given to demonstrate the necessity and efficiency of the proposed model.     

一种考虑稳定性的动态综合评价新模型

针对动态综合评价需要考虑被评对象的稳定性问题,提出了一种综合考虑指标权重、时间权重和稳定性的动态综合评价模型。定义了稳定因子来表征被评对象指标的稳定程度,采用离差最大化的方法确定指标权重,提出了一种基于极小范数时间权重确定方法。将所提模型应用于军事IP网络评价,结果表明该模型能够把被评对象的稳定性反映到评价结果中。     

A comprehensive model of human ear for analysis of implantable hearing devices

A finite element (FE) model of the human ear including the ear canal, middle ear, and spiral cochlea was constructed from histological sections of human temporal bone. Multiphysics analysis of the acoustics, structure, and fluid coupling in the ear was conducted in the model. The viscoelastic material behavior was applied to the middle ear soft tissues based on dynamic measurements of tissues in our laboratory. The FE model was first validated using the experimental data obtained in human cadaver ears, and then used to investigate the efficiency of the forward and reverse mechanical driving with middle ear implant, and the passive vibration of basilar membrane (BM) with cochlear implant placed in the cochlear scala tympani. The middle ear transfer function and the cochlear function of the BM vibration were derived from the model. This comprehensive ear model provides a novel computational tool to visualize and compute the implantable hearing devices and surgical procedures.