Numerical study of microbump failure in 3D microelectronic structures

Microbump failure in 3D microelectronic chip stacks is studied numerically using the finite element method. The microbump structure consists of a solder joint sandwiched between copper pads connected to through-silicon vias. The model system is subject to prescribed shear deformation, with possible superimposed tension or compression. A ductile damage model for solder is implemented to investigate failure propensity and cracking pattern as affected by the loading mode and underfill material. Failure of the solder is found to be sensitive to the loading mode, with a superimposed tension or compression on shear easily changing the crack path and tending to reduce the solder ductility.     

Random vibration reliability of BGA lead-free solder joint

Solder joint fatigue failure under vibration loading has been a great concern in microelectronic industry. High-cycle fatigue failure of lead-free solder joints has not been adequately addressed, especially under random vibration loading. This study aims to understand the lead-free solder joint behavior of BGA packages under different random vibration loadings. At first, non-contact TV Laser holography technology was adopted to conduct experimental modal analysis of the test vehicle (printed circuit board assembly) in order to understand its dynamic characteristics. Then, its first order natural frequency was used as the center frequency and narrow-band random vibration fatigue tests with different kinds of acceleration power spectral density (PSD) amplitudes were respectively carried out. Electrical continuity through each BGA package is monitored during the vibration event in order to detect the failure of package-to-board interconnects. The typical dynamic voltage histories of failed solder joints were obtained simultaneously. Thirdly, failed solder joints were cross-sectioned and metallurgical analysis was applied to investigate the failure mechanisms of BGA lead-free solder joints under random vibration loading. The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases. Solder joint failure locations are changed from the solder bump body of the PCB side to the solder ball neck, finally to the Ni/intermetallic compound (IMC) interface of the package side. The corresponding failure modes are also converted from ductile fracture to brittle fracture with the increase of vibration intensity.     

Underfill constraint effects during thermomechanical cycling of flip-chip solder joints

The presence of an “underfill” encapsulant between a microelectronic device and the underlying substrate is known to substantially improve the thermal fatigue life of flip-chip (FC) solder joints, primarily due to load-transfer from the solder to the encapsulant. In this study, a new single joint-shear (SJS) test, which allows the measurement of the strain response of an individual solder ball during thermomechanical cycling (TMC), has been used to investigate the impact of the constraint imposed by the underfill on a solder joint. Finite element (FE) modeling has been used to demonstrate that the SJS sample geometry captures most of the deformation characteristics of an FC joint and to provide insight into experimental observations. It has been shown that the strain response of a eutectic Pb-Sn solder joint is influenced significantly by in-situ microstructural coarsening during TMC, which in turn is dependent on the underfill properties. In general, underfill properties, which allow the imposition of large compressive-hydrostatic stresses on the solder joint, were the most effective in reducing coarsening. Phase coarsening prevented the stabilization of the stress-strain response of the solder, even in the absence of crack damage, and was found to depend strongly on the local inelastic-strain state within the joint. This necessitates that future solder deformation models account for strain-history-dependent microstructural evolution and that underfill properties be optimized to minimize the extent of coarsening during TMC in order to maximize joint life.     

Numerical study of ductile failure morphology in solder joints under fast loading conditions

A numerical study is undertaken to investigate solder joint failure under fast loading conditions. The finite element model assumes a lap-shear testing configuration, where the solder joint is bonded to two copper substrates. A progressive ductile damage model is incorporated into the rate-dependent elastic-viscoplastic response of the tin (Sn)–silver (Ag)–copper (Cu) solder alloy, resulting in the capability of simulating damage evolution leading to eventual failure through crack formation. Attention is devoted to deformation under relative high strain rates (1–100 s⁻¹), mimicking those frequently encountered in drop and impact loading of the solder points. The effects of applied strain rate and loading mode on the overall ductility and failure pattern are specifically investigated. It is found that, under shear loading, the solder joint can actually become more ductile as the applied strain rate increases, which is due to the alteration of the crack path. Failure of the solder is very sensitive to the deformation mode, with a superimposed tension or compression on shear easily changing the crack path and tending to reduce the solder joint ductility.     

Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.     

Digital image correlation for solder joint fatigue reliability in microelectronics packages

Digital image correlation (DIC) measurement of solder joint strain resulting from thermal cycling fatigue loading is reported in this study. The experimental measurements are compared to finite element analysis modeling of solder joint strain in a plastic ball grid array (PBGA) soldered assembly. The PBGA test sample was cross-sectioned and mounted in a thermal cycling chamber and subject to in-situ temperature cycling between 25 °C and 100 °C. The local solder joint strain range accumulated during temperature cycling was measured by the DIC technique. The in-plane inelastic strains in the solder joint accumulated after the 7th and the 14th thermal cycle were measured directly by the DIC system and computed by an element-based DIC analysis software developed by the author. Finite element analysis was conducted to simulate the loading used in the experiments and comparison was made to the experimental results. The measured and predicted displacement field patterns show satisfactory correlation and agreement.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Modified micro–macro thermo-mechanical modelling of ceramic ball grid array packages

The ceramic ball grid array (CBGA) packages are typically used for high I/O count area array assemblies. As the package size is large, the distance to neutral point is also high resulting in a large thermal deformation mismatch between the CBGA package and the printed circuit board (PCB). In order to cope with this problem, a special solder joint connection is used. As CBGA assemblies are used for high pin count assemblies, a full 3D thermo-mechanical modelling of an assembly to an FR4 board is not possible anymore. Therefore, a modified micro–macro methodology is proposed where only the critical solder joint is modelled in detail, while the other connections are replaced by equivalent connections. For several CBGA configurations, simulation results are correlated to thermal cycling test results. Finally, a parameter sensitivity study shows that the PCB properties have a significant influence on the solder joint reliability.     

Determination of Fracture Toughness of Underfill/Chip Interface With Digital Image Speckle Correlation Technique

The layered packages are prone to multimode damages and failures when they are subjected to complicated and coupling environmental loading. As a result, fracture toughness is usually used as a fracture criterion to evaluate the reliability of polymer/inorganic interface. In this study, an in-situ/real-time micro-digital image speckle correlation (mu-DiSC) system was established and employed to determine the fracture toughness of underfill/chip interface involved in flip chip assembly. The tests were carried out over a wide range of temperatures and at various loading angles. In order to verify the finding of the mu-DiSC technique, an interface fracture mechanics based finite element model is implemented into ANSYS to calculate the values of crack-tip opening displacement of underfill/chip joint under different loading configurations. The results obtained from the simulation are found to be in good agreement with those measured by the mu-DiSC system, indicating that the system can be used as an accurate and effective experimental tool for the electronic packages. The fractographs, with respect to different temperatures and loading angles, are further discussed     

Improved reliability of copper-cored solder joints under a harsh thermal cycling condition

This study simulated the performance of Cu-cored solder joints in microelectronic components subjected to the extreme thermal cycling conditions often encountered in the automobile industry by comparing the thermal cycling behavior of Cu-cored solder joints containing two different coating layers of Sn–3.0Ag and Sn–1.0In with that of a baseline Sn–3.0Ag–0.5Cu solder joint under a severe temperature cycling range of ?55 to +150 °C. Both Cu-cored solder joints can be considered a potential solution to interconnects in microelectronic semiconductor packages used under harsh thermal conditions on account of their greater resistance to thermal stress caused by the severe temperature cycling than the baseline Sn–3.0Ag–0.5Cu solder joint.     

Reliability model for bridging failure of Pb-free ball grid array solder joints under compressive load

The ever increasing power density in high performance microelectronic devices for applications such as large business computing and telecommunication infrastructure has led to several new reliability challenges for solder interconnects. One of them is the creep collapse and bridging of ball grid array (BGA) solder joints under heatsink compressive loads. For characterizing the solder joint response to compressive load and model the corresponding reliability failure, the compressive creep behavior of Sn3.8Ag0.7Cu solder was first investigated. A viscoplastic constitutive model developed from the creep characterization was then incorporated into numerical finite element (FE) analysis to predict solder joint creep collapse and bridging under heatsink compressive load. The numerical analysis results were validated by experimental studies of solder joint collapse under compressive load and isothermal aging condition. A simplified power-law formula is also provided for modeling the creep collapse of Sn3.8Ag0.7Cu solder joint. The model may be applied for predicting solder joint compressive reliability under a prescribed heatsink compression, or to determine the maximum allowable heatsink load for a given life expectancy.     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

Design of Experiments for Board-Level Solder Joint Reliability of PBGA Package Under Various Manufacturing and Multiple Environmental Loading Conditions

A design of experiments was conducted to determine the reliability of plastic ball grid array packages under various manufacturing and multiple environmental loading conditions. Parameters included conformal coating methods, underfill, solder mask defined, and non-solder mask defined pads. Board-level temperature cycling, vibration, and combined temperature cycling and vibration testing were performed to quantify the reliability and identify preferred design parameters. Through the main effects and interaction analysis, test results show underfill is the key parameter related to the solder joint reliability improvement. Conformal coat method and printed circuit board pad design are not main effects on solder joint reliability. No interactive relationship exists among these three factors under temperature cycling loading, but some interactive relationship between printed circuit board pad type and the conformal coating method exists under vibration and combined loading conditions.     

Solder interconnect reliability under drop impact loading conditions using High-speed Cold Bump Pull

The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA’s and navigation systems contain more and more functionality and smaller microelectronic components. Dropping an appliance during its lifespan is very common and the product is required to survive this. The drop however, generates significant forces and vibrations on the internal assembly of the product. The performance of a microelectronic component under drop conditions has thus become an important reliability parameter.Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing.Already many researchers have investigated new test techniques capable of replacing the drop impact test. In the CBP test the solder bump is pulled in vertical direction from the die using a small pair of jaws. In this test, by varying the pull speed several different strain rates can be applied to the solder bump.In our research a correlation between the drop impact test and Cold Bump Pull test is investigated. This can be divided into three parts. First by investigating the Cold Bump Pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the Cold Bump Pull test to investigate solder bump deformation and solder bump loading during pull off. Finally in a comparison the differences and similarities between the two tests are briefly discussed and some observations concerning the solder joint performance are presented.     

Finite element modeling of thermal fatigue and damage of solder joints in a ceramic ball grid array package

A nonlinear finite element model is presented for analyzing the cyclic and thermal fatigue loading and for viscoplastic damage characterization of the lead-tin (Pb-Sn) solder joints in a ceramic ball grid array (CBGA) surface mount package. An approach using a Δ ∈ _eq ⁱⁿ -modified Coffin-Manson equation is proposed to estimate the fatigue life of the solder joints. The Δ ∈ _eq ⁱⁿ represents a saturated equivalent inelastic strain range as determined by the finite element model. The present study shows that the predictied fatigue life and the associated damage mechanism of the solder joint agree reasonably well with the test data for the 18,25, and 32 mm CBGA packages run at a cyclic temperature load of 0°C/100°C with a frequency of 1.5 cycles per hour. Analysis also shows that a preferred failure site is expected to occur in and around the Pb37-Sn63 solder attachment of the solder joint. A time-dependent (creep induced) damage mechanism is found to be more pronounced than the time-independent (plastic deformation) mechanism.     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Rate-dependent properties of Sn-Ag-Cu based lead-free solder joints for WLCSP

The increasing demand for portable electronics has led to the shrinking in size of electronic components and solder joint dimensions. The industry also made a transition towards the adoption of lead-free solder alloys, commonly based around the Sn-Ag-Cu alloys. As knowledge of the processes and operational reliability of these lead-free solder joints (used especially in advanced packages) is limited, it has become a major concern to characterise the mechanical performance of these interconnects amid the greater push for greener electronics by the European Union.In this study, bulk solder tensile tests were performed to characterise the mechanical properties of SAC 105 (Sn-1%wt Ag-0.5%wt Cu) and SAC 405 (Sn-4%wt Ag-0.5%wt Cu) at strain rates ranging from 0.0088 s⁻¹ to 57.0 s⁻¹. Solder joint array shear and tensile tests were also conducted on wafer-level chip scale package (WLCSP) specimens of different solder alloy materials under two test rates of 0.5 mm/s (2.27 s⁻¹) and 5 mm/s (22.73 s⁻¹). These WLCSP packages have an array of 12 × 12 solder bumps (300 μm in diameter); and double redistribution layers with a Ti/Cu/Ni/Au under-bump metallurgy (UBM) as their silicon-based interface structure.The bulk solder tensile tests show that Sn-Ag-Cu alloys exhibit higher mechanical strength (yield stress and ultimate tensile strength) with increasing strain rate. A rate-dependent model of yield stress and ultimate tensile strength (UTS) was developed based on the test results. Good mechanical performance of package pull-tests at high strain rates is often correlated to a higher percentage of bulk solder failures than interface failures in solder joints. The solder joint array tests show that for higher test rates and Ag content, there are less bulk solder failures and more interface failures. Correspondingly, the average solder joint strength, peak load and ductility also decrease under higher test rate and Ag content. The solder joint results relate closely to the higher rate sensitivity of SAC 405 in gaining material strength which might prove detrimental to solder joint interfaces that are less rate sensitive. In addition, specimens under shear yielded more bulk solder failures, higher average solder joint strength and ductility than specimens under tension.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity