Stacked Ge islands for photovoltaic applications

Stacked Ge islands formed via the Stranski–Krastanov growth mode were incorporated into the intrinsic layer of Si-based pin diode to improve the performance of the solar cells in the near-infrared regime. The onset of the external quantum efficiency was extended up to around 1.4 mm for the solar cells with stacked Ge islands. The quantum efficiency was found to increase with increasing number of stacking, and the onset of the photocurrent response was in good agreement withroom-temperature photoluminescence energy of the Ge islands. These results manifest that the Ge islands did play a role toincrease the quantum efficiency. Furthermore, a part of electron-hole pairs generated within Ge islands was separated by the internal electric field and contribute to the photocurrent.     

Theory of the basic optoelectronic behavior of a tunnel diode

The basic behavior of a tunnel diode when it is used as an optoelectronic device is presented. It is shown that a tunnel diode can be used as an electro-optic modulator, as a device that exhibits self-induced transparency, or as a wavelength converter (for both upconversion and downconversion). The tunnel diode has optical bistability even if it is not placed inside a Fabry-Perot resonator. Numerical estimations are made for some of the parameters of interest for an optoelectronic device and are compared with those of other existing semiconductor-based optoelectronic devices. As the numerical estimates show, a tunnel diode can be a highly efficient optoelectronic device with an extremely wide area of application.     

Atomically controlled processing in silicon-based CVD epitaxial growth

One of the main requirements for Si-based ultrasmall device is atomic-order control of process technology. Here, we show the concept of atomically controlled processing for group IV semiconductors based on atomic-order surface reaction control in Si-based CVD epitaxial growth. Self-limiting formation of 1-3 atomic layers of group IV or related atoms after thermal adsorption and reaction of hydride gases on Si(1-x)Gex(100) (x = 0-1) surface are generalized based on the Langmuir-type model. Moreover, Si-based epitaxial growth on N, P or C atomic layer formed on Si(1-x)Gex(100) surface is achieved at temperatures below 500 degrees C. N atoms of about 4 x 10(14) cm(-2) are buried in the Si epitaxial layer within about 1 nm thick region. In the Si(0.5)Ge(0.5) epitaxial layer, N atoms of about 6 x 10(14) cm(-2) are confined within about 1.5 nm thick region. The confined N atoms in Si(1-x)Gex preferentially form Si-N bonds. For unstrained Si cap layer grown on top of the P atomic layer formed on Si(1-x)Gex(100) with P atomic amount of below about 4 x 10(14) cm(-2) using Si2H6 instead of SiH4, the incorporated P atoms are almost confined within 1 nm around the heterointerface. It is found that tensile-strain in the Si cap layer growth enhances P surface segregation and reduces the incorporated P atomic amount around the heterointerface. Heavy C atomic-layer doping suppresses strain relaxation as well as intermixing between Si and Ge at the nm-order thick Si(1-x)Gex/Si heterointerface. These results open the way to atomically controlled technology for ULSIs.     

Germanium‐Assisted Direct Growth of Graphene on Arbitrary Dielectric Substrates for Heating Devices

Direct growth of graphene on dielectric substrates is a prerequisite to the development of graphene‐based electronic and optoelectronic devices. However, the current graphene synthesis methods on dielectric substrates always involve a metal contamination problem, and the direct production of graphene patterns still remains unattainable and challenging. Herein, a semiconducting, germanium (Ge)‐assisted, chemical vapor deposition approach is proposed to produce monolayer graphene directly on arbitrary dielectric substrates. By the prepatterning of a catalytic Ge layer, the graphene with desired pattern can be achieved conveniently and readily. Due to the catalysis of Ge, monolayer graphene is able to form on Ge‐covered dielectric substrates including SiO₂/Si, quartz glass, and sapphire substrates. Optimization of the process parameters leads to complete sublimation of the catalytic Ge layer during or immediately after formation of the monolayer graphene, enabling direct deposition of large‐area and continuous graphene on dielectric substrates. The large‐area, highly conductive graphene synthesized on a transparent dielectric substrate using the proposed approach has exhibited a wide range of applications, including in both defogger and thermochromic displays, as already successfully demonstrated here.     

Hybrid integrated photodetector with flat-top steep-edge spectral response

Hybrid integrated photodetectors with flat-top steep-edge spectral responses that consist of an Si-based multicavity Fabry-Perot (F-P) filter and an InP-based p-i-n absorption structure (with a 0.2?μm In_0.53Ga_0.47As absorption layer), have been designed and fabricated. The performance of the hybrid integrated photodetectors is theoretically investigated by including key factors such as the thickness of each cavity, the pairs of each reflecting mirror, and the thickness of the benzocyclobutene bonding layer. The device is fabricated by bonding an Si-based multicavity F-P filter with an InP-based p-i-n absorption structure. A hybrid integrated photodetector with a peak quantum efficiency of 55% around 1549.2?nm, the -0.5 dB band of 0.43?nm, the 25?dB band of 1.06?nm, and 3?dB bandwidth more than 16?GHz, is simultaneously obtained. Based on multicavity F-P structure, this device has good flat-top steep-edge spectral response.     

Growth of silicon based germanium tin alloys

Germanium tin (GeSn) is under equilibrium a two phase (Ge + Sn) system. Single phase GeSn alloys are important for silicon based heterostructure devices as stressors for Ge channels and as candidates for direct/indirect band cross-over. Such alloys would allow superior Ge channel metal oxide semiconductor devices and optoelectronic infrared circuits on a Si substrate.Preparation of GeSn layers is possible at low growth temperatures. We discuss the challenges caused by the non-equilibrium growth and the limitations of low temperature epitaxy. Main challenges and limitations are the surface segregation, precipitations and defect accumulation in low temperature epitaxy.The problem of high lattice mismatch between Si and GeSn (> 4%) can be solved using virtual substrates with strain relaxed Ge buffer layers. The lattice mismatch can be reduced to 1% and below.Growth of pseudomorphic GeSn layers on Ge buffers/Si substrate was investigated. The samples were characterized by X-ray methods and Raman spectroscopy. High device process stability was achieved up to 600 °C annealing and documented by Raman spectroscopy. Fabrication of a detector test device demonstrated feasibility for optoelectronic applications with extended infrared range.     

Evolution of SiO2/Ge/HfO2(Ge) multilayer structure during high temperature annealing

Use of germanium as a storage medium combined with a high-k dielectric tunneling oxide is of interest for non-volatile memory applications. The device structure consists of a thin HfO₂ tunneling oxide with a Ge layer either in the form of continuous layer or discrete nanocrystals and relatively thicker SiO₂ layer functioning as a control oxide. In this work, we studied interface properties and formation kinetics in SiO₂/Ge/HfO₂(Ge) multilayer structure during deposition and annealing. This material structure was fabricated by magnetron sputtering and studied by depth profiling with XPS and by Raman spectroscopy. It was observed that Ge atoms penetrate into HfO₂ layer during the deposition and segregate out with annealing. This is related to the low solubility of Ge in HfO₂ which is observed in other oxides as well. Therefore, Ge out diffusion might be an advantage in forming well controlled floating gate on top of HfO₂. In addition we observed the Ge oxidation at the interfaces, where HfSiO_x formation is also detected.     

Chiro-Optoelectronic Encodable Multilevel Thin Film Electronic Elements with Active Bio-Organic Electrolyte Layer

It is suggested that chiral photonic bio-enabled integrated thin-film electronic elements can pave the base for next-generation optoelectronic processing, including quantum coding for encryption as well as integrated multi-level logic circuits. Despite recent advances, thin-film electronics for encryption applications with large-scale reconfigurable and multi-valued logic systems are not reported to date. Herein, highly secure optoelectronic encryption logic elements are demonstrated by facilitating the humidity-sensitive helicoidal organization of chiral nematic phases of cellulose nanocrystals (CNCs) as an active electrolyte layer combined with printed organic semiconducting channels. The ionic-strength controlled tunable photonic band gap facilitates distinguishable and quantized 13-bit electric signals triggered by repetitive changes of humidity, voltage, and the polarization state of the incident light. As a proof-of-concept, the integrated circuits responding to circularly polarized light and humidity are demonstrated as unique physically unclonable functional devices with high-level logic rarely achieved. The convergence between functional nanomaterials and the multi-valued logic thin-film electronic elements can provide optoelectronic counterfeiting, imaging, and information processing with multilevel logic nodes.     

A study of side gate test structures in InAlAs/InGaAs HEMTs for optoelectronic circuit applications

The InAlAs/InGaAs HEMT is a key electron device used in optoelectronic integrated circuits (OEICs) operating in the 1·3 and 1·5 μm optical wavelength ranges. OEIC performances can be degraded by side-gating effects associated with the HEMT. A side gate current is evidenced and demonstrated to be (i) due to a hole current induced by an impact ionization mechanism into the HEMT InGaAs channel and flowing through the InAlAs buffer layer and (ii) strongly dependent on the side gate test structure geometries and types of contacts. Finally, an optimized structure for monolithic integration is presented together with requirements on the operating point.     

Growth of Ge nanoparticles on SiO2/Si interfaces during annealing of plasma enhanced chemical vapor deposited thin films

Multilayer germanosilicate (Ge:SiO₂) films have been grown by plasma enhanced chemical vapor deposition. Each Ge:SiO₂ layer is separated by a pure SiO₂ layer. The samples were heat treated at 900 °C for 15 and 45 min. Transmission electron microscopy investigations show precipitation of particles in the layers of highest Ge concentration. Furthermore there is evidence of diffusion between the layers. This paper focuses mainly on observed growth of Ge particles close to the interface, caused by Ge diffusion from the Ge:SiO₂ layer closest to the interface through a pure SiO₂ layer and to the interface. The particles grow as spheres in a direction away from the interface. Particles observed after 15 min anneal time are 4 nm in size and are amorphous, while after 45 min anneal time they are 7 nm in size and have a crystalline diamond type Ge structure.     

Germanium epitaxy on silicon

With the rapid development of on-chip optical interconnects and optical computing in the past decade, silicon-based integrated devices for monolithic and hybrid optoelectronic integration have attracted wide attention. Due to its narrow pseudo-direct gap behavior and compatibility with Si technology, epitaxial Ge-on-Si has become a significant material for optoelectronic device applications. In this paper, we describe recent research progress on heteroepitaxy of Ge flat films and self-assembled Ge quantum dots on Si. For film growth, methods of strain modification and lattice mismatch relief are summarized, while for dot growth, key process parameters and their effects on the dot density, dot morphology and dot position are reviewed. The results indicate that epitaxial Ge-on-Si materials will play a bigger role in silicon photonics.     

硅基发光材料研究进展

硅基发光材料是光电子集成的基础材料。发光多孔硅是硅基发光材料的一个新进展，已实现了硅基光电子集成。随着多孔硅研究的深化和纳米科学的发展，硅基发光材料正向纳米方向开拓，与此同时，在新的理论认识与技术条件下，硅材料改性，杂质发光，缺陷工程和硅然异质外延也呈现出新的发展趋势。     

A fully tunable single-walled carbon nanotube diode

We demonstrate a fully tunable diode structure utilizing a fully suspended single-walled carbon nanotube. The diode's turn-on voltage under forward bias can be continuously tuned up to 4.3 V by controlling gate voltages, which is ～6 times the nanotube band gap energy. Furthermore, the same device design can be configured into a backward diode by tuning the band-to-band tunneling current with gate voltages. A nanotube backward diode is demonstrated for the first time with nonlinearity exceeding the ideal diode. These results suggest that a tunable nanotube diode can be a unique building block for developing next generation programmable nanoelectronic logic and integrated circuits.     

An Atomically Thin Optoelectronic Machine Vision Processor

2D semiconductors, especially transition metal dichalcogenide (TMD) monolayers, are extensively studied for electronic and optoelectronic applications. Beyond intensive studies on single transistors and photodetectors, the recent advent of large-area synthesis of these atomically thin layers has paved the way for 2D integrated circuits, such as digital logic circuits and image sensors, achieving an integration level of ≈100 devices thus far. Here, a decisive advance in 2D integrated circuits is reported, where the device integration scale is increased by tenfold and the functional complexity of 2D electronics is propelled to an unprecedented level. Concretely, an analog optoelectronic processor inspired by biological vision is developed, where 32 × 32 = 1024 MoS₂ photosensitive field-effect transistors manifesting persistent photoconductivity (PPC) effects are arranged in a crossbar array. This optoelectronic processor with PPC memory mimics two core functions of human vision: it captures and stores an optical image into electrical data, like the eye and optic nerve chain, and then recognizes this electrical form of the captured image, like the brain, by executing analog in-memory neural net computing. In the highlight demonstration, the MoS₂ FET crossbar array optically images 1000 handwritten digits and electrically recognizes these imaged data with 94% accuracy.     

Single-walled carbon nanotube thin film emitter-detector integrated optoelectronic device

We use the suspended single-walled carbon nanotube (SWNT) thin film technology to assemble the first prototype of an integrated optoelectronic SWNT device, a SWNT optocoupler in which a SWNT emitter and a SWNT detector couple two electrical circuits by the transmission of a signal through the optical channel. Our experiments show that the integrated SWNT emitter/SWNT detector is an ideal couple in which the broadband wavelength character of the emission matches the broadband detection capabilities.     

Light emission from high-k dielectrics containing Ge nanocrystals

A Ge light-emitting diode (LED) is demonstrated using a metal-insulator-semiconductor (MIS) tunneling structure with Ge nanocrystals (NCs) embedded within the insulator. A high-k dielectric insulator was used and the Ge NCs were grown by co-sputtering onto p-type Si substrates. Electron-hole radiative recombination within the Ge NCs (grown within HfAlO) allowed for the observation of infrared emission. Visible light was also detected due to defect-related radiative recombination at the Ge/HfAlO interface. The NC size and Ge content were measured using transmission electron microscopy (TEM), energy dispersive X-ray (EDX) spectroscopy and Raman spectroscopy. The peak wavelength from the photoluminescence experiments was lower when HfAlO was used as the dielectric than when HfO₂ was used. This is likely due to the larger band gap of HfAlO, when compared to HfO₂.     

氢化纳米硅薄膜光电性质及其应用研究进展

氢化纳米硅（nc-Si:H）薄膜具有室温下的高电导率、电致发光及光致发光等独特的性能，可应用于超大规模集成电路中，因而引起人们广泛的研究兴趣。简单地综述了国内外有关nc-Si:H薄膜的制备方法、导电机理、发光机理及其应用于量子功能器件等方面的研究工作。     

Pd-oxide- Al/sub 0.24/Ga/sub 0.76/As (MOS) high electron mobility transistor (HEMT)-based hydrogen sensor

An interesting hydrogen sensor based on an Al/sub 0.24/Ga/sub 0.76/As Schottky barrier high-electron mobility transistor with a catalytic Pd metal/oxide/semiconductor is fabricated and demonstrated. In comparison with traditional Schottky diodes or capacitance-voltage type hydrogen sensors, the studied device exhibits larger current variation, lower hydrogen detection limit, and shorter transient hydrogen response time. Besides, good hydrogen-sensing properties, such as significant drain current change, threshold voltage shift, and transconductance change of transistor behaviors, are obtained. Therefore, the studied device provides the promise for high-performance solid-state hydrogen sensors, optoelectronic integrated circuits, and microelectromechanical system applications.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.