The absorption ink transfer mechanism of gravure offset printing for electronic circuitry

The gravure offset method has been developed toward an industrially viable printing technique for electronic circuitry. In order to obtain the optimum ink resin for printing lines of required thickness (>5 /spl mu/m) of narrow lines (down to 25 /spl mu/m), several ink resin systems have been assessed in previous studies by the authors. The best printed results were obtained with a novel ink using a hydrocarbon resin. This ink did not comply with the traditional ink transfer mechanism based on evaporation of the solvent, but with a postulated new "absorption mechanism.".     

Fully solution-processed organic thin-film transistors by consecutive roll-to-roll gravure printing

A high-performance/flexible organic thin-film transistor (OTFT) is fabricated by using all-step solution processes, which are composed of roll-to-roll gravure, plate-to-roll gravure and inkjet printing with the least process number of 5. Roll-to-roll gravure printing is used to pattern source/drain electrodes on plastic substrate while semiconductor and dielectric layers are printed by consecutive plate-to-roll gravure printing. Finally, inkjet printing of Ag organometallic ink is used to pattern the gate electrode. The fabricated OTFT exhibits excellent electrical performance, field-effect mobility over 0.2 cm²/Vs, which is one of the best compared to the previous works. The deposition of a self-assembled monolayer on the source-drain electrodes results in a higher work function which is suitable for a p-type polymer semiconductor. Moreover, the formation of dense gate electrode line on hydrophobic dielectric is achieved by selecting suitable Ag ink.     

Fabrication of microvias for multilayer LTCC substrates

Advances in screen printing and photoimageable paste technologies have allowed low-temperature cofired ceramic (LTCC) circuit densities to continue to increase; however, the size of vias for Z-axis interconnections in multilayer LTCC substrates have been a limiting process constraint. In order to effectively exploit the 50-100-/spl mu/m line/spacing capabilities of advanced screen printing and photoimageable techniques, microvia technologies need to achieve 100 /spl mu/m and under in diameter. Three main steps in fabrication of microvias include via formation, via metallization or via fill, and layer-to-layer alignment. The challenges associated with the processing and equipment for the fabrication of microvias are addressed in this paper. Microvias down to 50 /spl mu/m in diameter with spacings as small as 50 /spl mu/m are achieved in 50-254-/spl mu/m-thick LTCC tape layers through the use of a mechanical punching system, whereas the minimum size of 75-/spl mu/m via/spacing is obtained using a pulse laser-drilling system in the LTCC tape layers with the same thicknesses as those for the punching test. The quality of punched microvias and laser-drilled microvias will be presented as well. Layer-to-layer alignment is crucial to the connection of vias in adjacent LTCC tape layers. Through a stack and tack machine with a three-camera vision system and an adjustable precision stage, less than 25-/spl mu/m layer-to-layer misalignment is achieved across a 114.3/spl times/114.3 mm (4.5/spl times/4.5 in) design area. In a six-layer LTCC test substrate (152/spl times/152/spl times/0.762 mm), microvias of 50, 75, and 100 /spl mu/m in diameter are successfully fabricated without the use of via catch pads. The cross section of fired microvias filled with silver conductor pastes at various locations of this substrate demonstrates a minor layer-to-layer misalignment in both X and Y directions across the substrate.     

Roller-type gravure offset printing of conductive inks for high-resolution printing on ceramic substrates

The use of gravure offset printing methods at an industrial level requires a wide and deep knowledge of the printing properties of the inks. Novel hydrocarbon inks were developed with superior printing properties compared to alternative ethyl cellulose-based inks. There are principal behaviour properties of these inks that can be generally described. In particular, the resistance dependence of printed mass for single and multiprints and on the other hand, the effect of multiprinting on printed area smoothness and line height.

This article summarizes the results obtained and describes printing properties and defects: line widening, hair formation, ink flow from the gravure grooves, pinholes, image distortions, ribbing, scooping, streaking and gravure groove blocking. Three different printed samples were demonstrated, which are best suited for this manufacturing method: interdigital capacitor, inductor coil and laser soldering substrates.     

硅基板激光微熔覆电子浆料制备导体的研究

激光微细熔覆电子浆料技术是一种新型的柔性布线技术，采用激光精密加工系统对电子浆料进行处理以制备导线，具有柔性化程度高、电路图形设计、修改简捷、适合小批量生产等优点。特别是可以制备最小线宽为20 μm左右的导体，突破了传统丝网印刷工艺制备导线宽度的极限。利用激光微细熔覆工艺在单晶硅基板上制备出了银导线。所制备导线的最小宽度在30 μm左右，其电阻率和块状银在同一个数量级，能够满足应用要求。利用悬挂法测定其与硅基板的结合强度在兆帕数量级，与传统丝网印刷工艺相当。相关的工艺实验还表明，导体线宽随激光功率密度的增加而增加，随激光扫描速度的增加而减小;对于特定厚度的浆料预置层，激光扫描参数存在一个最佳的范围。激光扫描之后的高温热处理工艺有利于导线导电性能及其与硅基板的结合强度的进一步提高。     

Polymer film deposition with fine pitch openings by stencil printing

It is confirmed that stencil printing with a novel developed printable polyimide paste can be used for polymer film deposition on LSI wafers. A thick polyimide film with openings for solder ball bumping can be deposited on all of the LSIs on a wafer by stencil printing at one time. This stencil printing process does not need an expensive lithography process, providing cost-effective wafer-level chip scale packages (WLCSPs). In this study, a novel polyimide paste was tailored to have a higher thixotropy ratio than conventional printable polyimide materials. The novel printable polyimide paste shows that the viscosity ratio of more than 3.5 at the shear rate of 1 to 10 s⁻¹ and that the viscosity increases rapidly after the shear rate is lowered. Fine spaces of 40 μm between 250 μm openings were obtained for 10 μm thick polyimide films on Si wafers. It has been also confirmed that the new paste shows the variation range of 30 μm at the opening size of 385 μm within 100 continuously printed wafers. Even after the new paste was shear-thinned repeatedly, rheological behavior of the new paste was not changed. This robustness leads to higher efficiency of the materials for mass-producing. From the reliability viewpoint of the printed polyimide films, no peelings were observed on plasma-CVD SiN films after the pressure cooker test under the condition of 127 °C and 0.25 MPa with the humidity of 100% for 300 h. The optimal stencil printing process using the novel developed paste will lead to significant cost reduction of a patterned polymer deposition process. Finally, WLCSPs using the stencil printing of the new polyimide paste have been demonstrated for SRAM LSIs on 8-in. wafers.     

Optimisation of silver paste for flexography printing on LTCC substrate

The originality of this work consists in printing on ceramic tapes conductive silver tracks that reach a low resistivity by flexography process. Flexography is a solution for the mass production of multimaterial microdevices offering a huge potential of commercialisation in the near future. In order to test the flexography printing process for microelectronic application on Low Temperature Cofired Ceramic (LTCC) tapes, a screen printing paste was optimised to reach flexography printing requirements. Ink with 30% silver per weight was prepared and printed by flexography, roll to roll (R2R) process, on LTCC substrates. Three to five print passes were performed. Printed lines were sintered during 10 min at a peak temperature of 850 °C under normal air atmosphere. Conductive lines, with a mean width of 190 μm, a mean thickness of 1.50 μm and a resistivity of 2.8 × 10^?8 Ω m close to bulk silver resistivity, were achieved after sintering.     

Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon

The loss mechanisms of silicon coplanar waveguides (CPW) with aluminum metallization are investigated up to 40 GHz. Three main parts contribute to the attenuation of coplanar waveguides (CPWs): the frequency-dependent conductor losses of the metallization, frequency-independent substrate losses, and the specifically investigated bias-dependent interface losses caused by free charges at the Si-SiO/sub 2/ interface. The minimum losses found in 50-/spl Omega/ CPWs with 45-/spl mu/m signal line width were 0.19 db/mm at 10 GHz and 0.33 dB/mm at 40 GHz. High-purity silicon from a float zone (FZ) process was used as substrate. Substrates with lower purity from a Czochralski (CZ) process (resistivity 50-100 /spl Omega/cm) resulted in somewhat higher (0.2-0.3 dB/mm) losses for the same CPW geometry.     

High Power Conversion Efficiency of 13.61% for 1 cm2 Flexible Polymer Solar Cells Based on Patternable and Mass-Producible Gravure-Printed Silver Nanowire Electrodes

With the aim of developing high-performance flexible polymer solar cells, the preparation of flexible transparent electrodes (FTEs) via a high-throughput gravure printing process is reported. By varying the blend ratio of the mixture solvent and the concentration of the silver nanowire (AgNW) inks, the surface tension, volatilization rate, and viscosity of the AgNW ink can be tuned to meet the requirements of gravure printing process. Following this method, uniformly printed AgNW films are prepared. Highly conductive FTEs with a sheet resistance of 10.8 Ω sq⁻¹ and a high transparency of 95.4% (excluded substrate) are achieved, which are comparable to those of indium tin oxide electrode. In comparison with the spin-coating process, the gravure printing process exhibits advantages of the ease of large-area fabrication and improved uniformity, which are attributed to better ink droplet distribution over the substrate. 0.04 cm² polymer solar cells based on gravure-printed AgNW electrodes with PM6:Y6 as the photoactive layer show the highest power conversion efficiency (PCE) of 15.28% with an average PCE of 14.75 ± 0.35%. Owing to the good uniformity of the gravure-printed AgNW electrode, the highest PCE of 13.61% is achieved for 1 cm² polymer solar cells based on the gravure-printed FTEs.     

A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology

For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured.     

Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.     

Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-/spl mu/m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 /spl mu/m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.     

Direct fabrication of electric components on insulated boards by laser microcladding electronic pastes

In this paper, a novel method to fabricate the electronic components directly on insulating boards such as glass, ceramics, and organic laminated boards by laser microcladding electronic pastes was reported. With computer-aided design/computer-aided manufacturing (CAD/CAM) capability, the conductive metal lines and resistors with different patterns were fabricated successfully by this technique without mask. The experimental results demonstrated that the fabricated conductive lines and resistors have the same properties as those made by conventional thick-film methods and were bonded very well with the substrate. The minimum widths of the conductive lines on ceramic board, glass board, and printed circuit board can reach 20, 40, and 80 /spl mu/m, correspondingly. The maximum rates for laser microcladding can be beyond 50 mm/s. Some typical examples of circuit boards fabricated by this method were illustrated.     

Printed microinductors on flexible substrates for power applications

A low-profile microinductor was fabricated on a copper-clad polyimide substrate where the current carrying coils were patterned from the existing metallization layer and the magnetic core was printed using a magnetic ceramic-polymer composite material. Highly loaded ferrite-polymer composite materials were formulated, yielding adherent films with 4/spl pi/M/sub s//spl ap/3900 G at +5000 Oe applied DC field. These composite magnetic films combine many of the superior properties of high temperature ceramic magnetic materials with the inherent processibility of polymer thick films. Processing temperatures for the printed films were between 100/spl deg/C and 130/spl deg/C, facilitating integration with a wide range of substrates and components. The quality factor of the microinductor was found to peak at Q=18.5 near 10 MHz, within the optimal frequency range for power applications. A flat, nearly frequency independent inductance of 1.33 /spl mu/H was measured throughout this frequency range for a 5 mm/spl times/5 mm component, with a DC resistance of 2.6 /spl Omega/ and a resonant frequency of 124 MHz. The combination of printed ceramic composites with organic/polymer substrates enables new methods for embedding passive components and ultimately the integration of high Q inductors with standard integrated circuits for low profile power electronics.     

微型喷嘴雾化直写技术制备厚膜导体研究

采用微细雾化喷射沉积直写的方法在陶瓷基板上制备银厚膜导体。主要研究了施加气压、喷嘴到基板距离、直写速度以及雾化气压对导体线宽的影响规律,分析了微型喷嘴雾化直写厚膜导体机理,并优化了工艺参数,得到了最佳工艺参数范围:施加驱动气压控制在0.05~0.10 MPa,喷嘴到基板距离0.4~1.2 mm,直写速度在15 mm/s以下,雾化气压0.14~0.24 MPa,所得线宽350~750μm,单层膜厚1.5~10μm。     

Megahertz-class printed high mobility organic thin-film transistors and inverters on plastic using attoliter-scale high-speed gravure-printed sub-5 μm gate electrodes

High performance organic thin-film transistors and inverters operating at MHz frequencies at 10 V are fabricated on plastic with high throughput (printing speed up to 1.0 m/s) using attoliter-scale high-speed gravure printing. The high performance of the devices is achieved using highly scaled gravure printed features (smaller than 5 μm) and optimizing a high mobility organic semiconductor for the short-channel gravure printed devices (>0.5 cm²/V s) to realize record performance levels.     

A device transfer process "selectively occupied repeated transfer (SORT)" for resource-saving integration of polymer micro optics fabricated by "built-in mask" method

The device transfer process known as selectively occupied repeated transfer, which integrates thin-film device elements into a substrate with desired arrangement at one time using all-photolithographic methods, is demonstrated here. As the elements, 300-/spl mu/m-diameter polymer waveguide lenses made of acrylic photo-definable material are formed on a poly-vinyl-alcohol (PVA)-coated glass substrate in a two-dimensional array with 450-/spl mu/m pitch by UV light exposure through a "built-in mask." The lenses are transferred to a supporting substrate by solving the PVA in water, and are further transferred to a final substrate, on which catch-up sites that have stronger adhesion strength than the surrounding area are formed with a pitch of 1800 /spl mu/m. Selective transfer of the lens to the catch-up site is observed.     

An aqueous developable photoimageable silver conductor composition for high density electronic packaging

In our preliminary work, we have formulated aqueous developable photoimageable thick film conductor pastes, consisting of ‘inhouse processed’ submicron sized silver powders (functional material), micron sized lead borosilicate glass frits (permanent binder), epoxy acrylate resin with pendant –COOH group (base photoimageable polymer/temporary binder/organic vehicle) and 2,2′-dimethoxy-2-phenylacetophenone (photoinitiator). The conductor pastes thus formulated were manually screen printed on the alumina substrates, dried, exposed to the ultra-violet light through the desired test patterns, developed in a 1% aqueous sodium carbonate solution, and subjected to a standard one-hour thick film firing cycle. Solid content of the polymer appears to influence the paste performance. Prima facie observations indicate that the paste with the organic:inorganic ratio of 28:72 (corresponding to solid content of 89.9% of the polymer system) exhibits better electrical conductivity, relatively smooth surface finish and line/space resolution of 100 μm with ±5 μm accuracy. Investigations related to the effect of glass content on the properties of photoimageable conductor paste are also furnished in this communication.