A sequential soft-decision decoder for Reed-Solomon codes appliedto encoded PSK in Rayleigh-fading channels

A soft-decision stack algorithm with a variable-bias-term branch metric and accurate channel state information estimate is applied to a Reed-Solomon-encoded phase-shift keying (PSK) system in the presence of memoryless Rayleigh fading. To compensate for the variable decoding delay inherent in sequential decoding algorithms, a time-out mechanism is used by the inner decoder: if a time-out occurs before complete decoding of a given block, the decoder declares an erasure. An erasures-and-errors correction decoding algorithm is implemented at the outer decoder to recover any incorrect or incompletely decoded inner code words. Simulation results show that significant improvement over uncoded modulation can be achieved with this approach with moderate cost in decoding complexity     

A simple taboo-based soft-decision decoding algorithm for expandercodes

We present a simple soft-decision decoding algorithm that modifies Sipser and Spielman's (see IEEE Trans, Inform. Theory, vol.42, p.1710-22, Nov. 1996) hard-decision sequential “bit-flipping” algorithm for decoding expander codes. The algorithm incorporates symbol reliability information and a simple “taboo” function that avoids repeated flipping of the same bit. The two algorithms have comparable simplicity, but simulations show that the soft-decision algorithm results in both improved performance and-because fewer decoding iterations are necessary-improved speed     

A fast LDPC encoder/decoder for small/medium codes

Although Low-Density Parity-Check (LDPC) codes perform admirably for large block sizes — being mostly resilient to low levels of channel SNR and errors in channel equalization — real time operation and low computational effort require small and medium sized codes, which tend to be affected by these two factors. For these small to medium codes, a method for designing efficient regular codes is presented and a new technique for reducing the dependency of correct channel equalization, without much change in the inner workings or architecture of existing LDPC decoders is proposed. This goal is achieved by an improved intrinsic Log-Likelihood Ratio (LLR) estimator in the LDPC decoder — the ILE-Decoder, which only uses LDPC decoder-side information gathered during standard LDPC decoding. This information is used to improve the channel parameters estimation, thus improving the reliability of the code correction, while reducing the number of required iterations for a successful decoding. Methods for fast encoding and decoding of LDPC codes are presented, highlighting the importance of assuring low encoding/decoding latency with maintaining high throughput. The assumptions and rules that govern the estimation process via subcarrier corrected-bit accounting are presented, and the Bayesian inference estimation process is detailed. This scheme is suitable for application to multicarrier communications, such as OFDM. Simulation results in a PLC-like environment that confirm the good performance of the proposed LDPC coder/decoder are presented.     

从IS95 CDMA/1X的建设经验来看WCDMA无线网络规划

总结了IS95 CDMA／IX建设中经验与教训，阐述了WCDMA系统建设规划初期应考虑的关键要素并进行了分析。     

Analysis of an up/down power control algorithm for the CDMA reverselink under fading

We analyze the performance of a code division multiple access (CDMA) reverse link a with an up/down power control algorithm in the presence of fading. We derive a stochastic nonlinear feedback control system model for the power controlled reverse link, and study the power control performance based on the nonlinear model using the technique of statistical linearization. We provide a general analysis framework that allows us to study the effect of mobile speed, power control step size, and fading channel parameters such as correlation coefficient and rate of fading on power control errors. Numerical results show excellent accuracy of our analysis, which can be used to design and optimize the system parameters without going through lengthy simulations. For example, in the presence of shadow fading, it is seen that a power control step size in the range of 0.5-1.3 dB is sufficient to keep power control errors near a minimum. In the case of Rayleigh fading, the standard deviation of power control errors grows quickly even at moderate mobile speeds     

A new architecture for the Viterbi decoder for code rate k/n

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time     

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2-μm CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW     

一种利用约束Viterbi算法改进IS95协议信道编码的方法

IS95具有两个速率集,在同一个速率集中,不同的速率其数据帧的长度不同,为了使进入正交调制的数据帧的长度相同,其采用了信号重复器.信号重复器进行简单的重复作用,使得带宽不能充分利用.文中提出的方法利用一个信号发生器,产生已知的信号进入卷积编码,卷积编码后的数据帧长度同样符合要求,而信号发生器产生的已知信号在译码端可以作为译码时的约束条件进行约束Viterbi译码.在BSC信道模型的仿真结果证明,其在较高误码率的情况下具有较好的性能.     

从GSM、IS95 CDMA/1x的建设经验来看WCDMA无线网络规划

本文详尽地阐述了WCDMA系统建设规划初期应考虑的关键要素并进行了深入的分析,同时总结了IS95CDMA/1x建设中经验与教训,以期在WCDMA建设中予以借鉴,最后给出了建议的网络规划流程.     

A multi-D trellis decoder for A 155 Mb/s concatenated codec

An implementation of a 16 state, rate 8/9 six-dimensional (6-D) 8PSK rotationally invariant trellis decoder for use in a concatenated codec is described. The concatenated codec allows transmission of STM-1 signals (at the 155.52 Mb/s information rate) over a 72 MHz satellite transponder. The inner trellis decoder is used with an outer (255,239) RS block decoder. The trellis decoder operates at 165.93 Mb/s and currently has an implementation loss of only 0.2 dB. The concatenated codec achieves a bit error ratio of 10^?10 at an Eb/N⁰ of 8.2 dB (assuming an ideal modem and AWGN channel). Details are given of many Viterbi decoding ‘tricks’ that were used in order to implement the main functions of the decoder on two 10,000 gate equivalent CMOS programmable gate arrays.     

Multiuser Detection for Out-of-Cell Cochannel Interference Mitigation in the IS–95 Downlink

This paper considers the application of multiuser detection techniques to improve the quality of downlink reception in a multi-cell IS–95 digital cellular communication system. In order to understand the relative performance of suboptimum multiuser detectors including the matched filter detector, optimum multiuser detection in the context of the IS–95 downlink is first considered. A reduced complexity optimum detector that takes advantage of the structural properties of the IS–95 downlink and exhibits exponentially lower complexity than the brute-force optimum detector is developed. The Group Parallel Interference Cancellation (GPIC) detector, a suboptimum, low-complexity multiuser detector that also exploits the structure of the IS–95 downlink is then developed. Simulation evidence is presented that suggests that the performance of the GPIC detector may be near-optimum in several cases. The GPIC detector is also tested on a snapshot of on-air data measured with an omnidirectional antenna in an active IS–95 system and is shown to be effective for extracting weak downlink transmissions from strong out-of-cell cochannel interference. The results of this paper suggest that the GPIC detector offers the most performance gain in scenarios where weak downlink signals are corrupted by strong out-of-cell cochannel interference.     

A programmable decoder for Reed-Solomon codes

A programmable decoder for Reed-Solomon codes is described. The decoder is constructed using the Am2900 family of bit-slice elements and it is designed to perform error-correction erasure-filling decoding. The decoding rates obtained, lie in the range of 87 to 22 kilobits per second depending on the code and the error-erasure pattern encountered     

A 500-Mb/s soft-output Viterbi decoder

Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-/spl mu/m CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm/sup 2/ chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.     

A 40 Mb/s soft-output Viterbi decoder

Soft-output decoding has evolved as a key technology for new error correction approaches with unprecedented performance as well as for improvement of well established transmission techniques. In this paper, we present a high-speed VLSI implementation of the soft-output Viterbi algorithm, a low complexity soft-output algorithm, for a 16-state convolutional code. The 43 mm² standard cell chip achieves a simulated throughput of 40 Mb/s, while tested samples achieved a throughput of 50 Mb/s. The chip is roughly twice as big as a 16-state Viterbi decoder without soft outputs. It is thus shown with the design that transmission schemes using soft-output decoding can be considered practical even at very high throughput. Since such decoding systems are more complex to design than hard output systems, special emphasis is placed on the employed design methodology     

用FPGA实现IS-95A CDMA前向信道中的基带滤波器

介绍了IS-95A前向信道使用的基带滤波器,利用MATLAB软件对滤波器的系数量化进行了计算和仿真。FPGA的使用使得滤波器实现比较简单,而且具有高度的扩展性。     

A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.     

OCDMA通信系统编/解码器技术

介绍了光延迟线编／解码器，给出了两种光延迟线变址方案并分析了它们的性能。提出了三种新的编／解码器设计方案：基于步进啁啾FBG(光纤布喇格光栅)的光谱编码器、二维光延迟线编／解码器和多FBG编/解码器。     

光CDMA编解码器的误差分析

对光CDMA编解码器在的误差及其对系统误码率的影响进行了分析,研究了表明：对于时间编码系统,编解码器的误差都将引起信噪比的损失而导致误率上升;光谱编码系统受误差的影响要比时间编码系统大;光谱编码系统的可容纳用户数比时间编码系统多,误码率也低得多。     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented